Circuits and technologies for implantable biomedical devices

Biological processes such as neuronal signaling and cell growth are among the most complex micro- and nano-scale processes in nature. Historically such processes have been studied at the system level because there were no tools available to study individual components of the process. However, cellular-level interfacing is needed to provide a better understanding of the brain and to develop more advanced prosthetic devices and brain-machine interfaces. With semiconductor technology innovations, much recent work has been focused on unraveling biological complexity, but also on driving new diagnoses, treatments, and therapies that are tailored to the individual. One of the drivers behind those innovations is novel CMOS circuits enabling multi-modal, high-precision data collection and analysis at ultra-low power consumption. In this talk, I will present recent biomedical developments based on silicon technology, and I will discuss the requirements, materials, circuit techniques, and design challenges of their ASIC and SoC platforms.

 

Carolina Mora Lopez received her Ph.D. degree in Electrical Engineering in 2012 from the KU Leuven, Belgium, in collaboration with imec, Belgium. From 2012 to 2018, she worked at imec as a researcher and analog designer focused on interfaces for neural-sensing applications. During this time, she was the lead analog designer and project leader of the Neuropixels development project which resulted in the conception and fabrication of the Neuropixels 1.0 and 2.0 neural probes. She is currently the principal scientist and team leader of the Circuits & Systems for Neural Interfaces team at imec, which develops circuits and technologies for electrophysiology, neuroprosthetics and BMI. Her research interests include analog and mixed-signal circuit design for sensor, bioelectronic and neural interfaces. Carolina is a senior IEEE member and serves on the technical program committee of the ISSC conference, ISSCC SRP, VLSI circuits symposium, and ESSCIRC conference.

 

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Integrated Circuits and Systems for Immersive Connectivity and Sensing–ICS2

We are heading to an exciting world where the boundaries between the physical world and the digital/virtual world are blurring, and opportunities and possibilities that are unseeable today will be unleashed. This fascinating future world requires drastic technological breakthroughs and innovations. One key requirement is immersive connectivity and sensing with everything. In this talk, I will present our group research activities in integrated circuits and systems advancing this mission in three key pillars: wireline communication/interconnect, sensing, and wireless communication and radar.

 

Dr. Qun Jane Gu received a Ph.D. from the University of California, Los Angeles in 2007. After a couple of years of industry experience, she started her academic career in 2010 at the University of Florida. Since 2012, she has been with the University of California, Davis, where she is currently a professor. Dr. Jane Gu’s group is passionate in high performance RF, mm-wave and THz integrated circuits and systems and its broad applications. The works from her group have won nine best paper awards from international conferences, including four times from IEEE MTT-S International Microwave Symposium (IMS). She has received 2013 NSF CAREER award, 2015 UC Davis Outstanding Junior Faculty Award, 2017 and 2018 Qualcomm Faculty Award, 2019 UC Davis Chancellor Fellow, and 2022-23 Solid-State Circuits Society Distinguished Lecturer. She is a TPC member of solid state conferences RFIC, CICC and ISSCC.

 

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Optimizing Emerging Graph Applications Using Hardware-Software Co-Design

A graph is a ubiquitous data structure that models entities and their interactions through the collections of nodes and edges. It is widely employed in several important application domains ranging from social media, navigation tools, search engines, physics simulations, and biology. Despite its prevalence, the performance of graph workloads on commercial platforms is limited. This is mainly due to the irregular nature of memory accesses and convoluted control flow instructions used in graph applications while accessing large amounts of real-world graph data (i.e., billions of nodes/edges). Therefore, there is a pressing need for optimizing the performance of graph workloads.

In this talk, I will present a systematic optimization study of graph workloads running on both static and dynamic graphs. Specifically, I will present two of my most recent works called NDMiner [ISCA 2022] and Mint [MICRO 2022] in detail. NDMiner optimizes the execution of the Graph Pattern Mining (GPM) application. In this work, I will showcase how to combine the benefits of Near Data Processing (NDP) and domain specialization to improve GPM workload performance. Mint, on the other hand, investigates and optimizes a pattern mining application on temporal graphs (a type of dynamic graph), called temporal motif mining. Mint presents a new programming model, hardware accelerator architecture, and domain-specific optimization to significantly improve the performance of mining temporal motifs. In addition to these works, I will briefly tough upon our optimization and detailed benchmarking effort for traditional graph processing algorithms (e.g., PageRank and SSSP) and random walk-based graph learning pipelines (e.g., node classification and link prediction).

 

Nishil Talati recently completed his PhD from University of Michigan, USA. Prior to joining the PhD program, he completed a master’s degree with thesis from Technion, Israel, and an undergraduate degree from BITS Pilani, India. Nishil’s research interests span computer architecture, compilers, and software engineering. Specifically, he has worked on several optimization efforts to improve the memory performance of modern computing systems. One of his recent works was recognized as the best paper award at HPCA 2021.

 

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Prof. Filip Tavernier

Using CMOS for Optical Communication

I will discuss the challenge of using CMOS chips in optical communication applications in this talk. Optical communication has many advantages compared to copper and wireless systems. However, the optical-electrical conversion in the receiver typically requires an external photodiode adding volume and cost to the system. I will explain how it is possible to realize fully integrated optical receivers in CMOS using a pn-photodiode or a Schottky photodiode. While the former is only sensitive to 850 nm light, the latter is sensitive to the more abundant 1310 nm and 1550 nm wavelengths. Due to the intrinsically low response of these integrated photodiodes, low-noise readout circuits are required, which I will also discuss.

 

Filip Tavernier obtained the M.Sc. degree in Electrical Engineering and the Ph.D. degree in Engineering Science from KU Leuven, Leuven, Belgium, in 2005 and 2011, respectively. During 20112014, he was Senior Fellow in the microelectronics group at the European Organization for Nuclear Research (CERN) in Geneva, Switzerland. He was involved in chip designs for the upgrade program of the Large Hadron Collider (LHC) experiments. In 2014, he rejoined KU Leuven at the Department of Electrical Engineering (ESAT-MICAS). As of October 2015, he has been a professor within the same department. His main research interests include circuits for optical communication, data converters, DC-DC converters, and chips for cryogenic environments. Filip is a member of the technical program committees of ESSCIRC, CICC, and SBCCI. He has been SSC-L Guest Editor and is the current SSCS Webinar Chair.

 

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All-Digital Phase-Locked Loops (ADPLL)

047003 – All-Digital Phase-Locked Loops (ADPLL)

October  19,20,23  2022

Auditorium 1003, Mayer Bld.

Professor Robert Bogdan Staszweski, University College Dublin, Ireland  

 

Instructor: Prof. Robert Bogdan Staszweski
Teaching assistant: Itamar Melamed
Lectures: 13 hours, 3 days
Academic points: 1pts
Exam: TBD
Course Fee : 1700$ (see membership options)

For registration click here 

*Registration is open until August 18, 2022

 

Course Content:

The past two decades has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and highperformance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer
function precision, settling speed, frequency modulation capability, and amenability to integration with
digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also
exhibits advantages of better performance, lower power consumption, lower area and cost over the
traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced
by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional
phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for
detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an
analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits
are readily estimated and compensated using “free” but powerful digital logic.

Topics per Day:

Days 1 & 2: (7 academic hours) All-Digital Phase-Locked Loop (ADPLL)
Architecture and Implementation
This lecture presents a system-level view of the ADPLL.
1. Principles of phase-domain frequency synthesis
2. ADPLL closed-loop behavior
3. Direct frequency modulation of ADPLL
4. Alternative TX architectures using ADPLL and PA regulator
5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design

Day 3 Morning (3 academic hours): Digitally-controlled oscillator (DCO)
A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based
on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but
with a significant difference in one of the components: instead of continuously tuned varactor (variable
capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed
in either high or low capacitative state. The composite varactor performs digital-to-capacitance
conversion. This lecture presents a circuit and system level views of DCO.

Day 3 Afternoon (3 academic hours): Time-to-digital converter (TDC)
A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital
variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase
is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay
(about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level
implementation issues.

Prerequisites:

  • 044137 Electronic Circuits
  • 044202 Random Signals

Grading:

Written exam – 100%

Recommended Literature and Study Materials:

Book: R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New
Jersey: John Wiley & Sons, Inc., Sept. 2006. ISBN: 978-0471772552.

Instructor’s Bio:

Robert Bogdan Staszewski received the BSc (summa cum laude), MSc and PhD degrees from the University
of Texas at Dallas in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel Network
Systems in Richardson, TX, USA, working on SONET cross-connect systems for fiber optics
communications. He joined Texas Instruments in Dallas, TX, USA, in 1995 where he was elected
Distinguished Member of Technical Staff (2% of the technical population). Between 1995 and 1999, he
was engaged in advanced CMOS read channel development for hard disk drives. In 1999 he co-started a
Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally intensive
approaches to traditional RF functions for integrated radios in deep-submicron CMOS. He served as a CTO
of the DRP group between 2007 and 2009. In 2009, he joined Delft University of Technology in the
Netherlands where he is currently a guest Full Professor. Since 2014, he has been a Full Professor with
University College Dublin in Ireland. He has authored and co-authored seven books, 11 book chapters,
160 journal and 220 conference publications, and holds 220 issued US patents. His research interests
include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers,
as well as quantum computers. He is an IEEE Fellow and recipient of IEEE Circuits and Systems Industrial Pioneer Award.

For registration click here

*Registration is open until August 18, 2022

 

 

Reliability of Semiconductor Devices

046003 – Reliability of Semiconductor Devices

September  18-20, 2022

Auditorium 280, Mayer Bld.

Dr. Eitan Shauly, Tower Semiconductor  

 

Instructor: Dr. Eitan Shauly
Teaching assistant: Efrat Ordan
Lectures: 13 hours, 3 days
Academic points: 1pts
Exam: TBD
Course Fee : 1700$ (see membership options)

For registration click here 

*Registration is open until August 18, 2022

 

Sylabus:

Detailed overview of reliability failure mechanisms and modeling, from the foundry perspective. Covered Physical and Environmental FEOL and BEOL qualification, Automotive.

Topics:

1 Introduction to Reliability and time degradation

Quality and Reliability; The Reliability bathtub

Failure in time and the acceleration factors (Temp, Voltage, Currents stress)

MTTF (Mean-time-to-Failure), MTBF (Mean-time-between-Failure), FIT (Failure-in-time)

Materials and device degradation vs time – modeling, Competing degradation mechanisms,

Definition of quality and reliability; Yield vs Reliability; Reliability Scaling,

Physical failure mechanisms (Intro): HCI, NBTI, EM, SM, ESD,; Latchup, Soft error

2 EM=Electromigration

Introduction-BEOL reliability concerns; Electromigration–definition; Mass motion and flux modeling; Blech length; Void formation; Stress effects

EM testing and qualification;

Grain Size dependency, Alloys, Barrier metals and other process related performances improvement, N7 and N5 BEOL solutions

EM LT as function of Width and length

EM under AC vs DC conditions; EM scaling limitations

3 SM = Stress Migration in solid Materials

Stress migration, void formation and growth

Stress migration modeling w/ and w/o dielectric all—around

Physics of stress migration; Nucleation; Activation diffusion volume

Resistance change due to voids growth, stress gradients

SIV = Stress-Induced-Voids

SIV modeling;

Layout solution, double via solution; Stacked via sensitivity, effect of misalignment

BEOL dielectric cracking

SM and SIV qualification

4 HCI=Hot Carrier Injection

Carriers’ mobility; currents and voltages in MOSFET under operation: Vt, Id, Ib, Is, CLM, SCE, DIBL,

HCI – mechanism and modeling; DAHC (Drain Avalanche Hot carrier), CHE (Channel hot Electron), SHE (Substrate Hot Electron), others; Lucky Electron Model,

Interface charge generation,

HCI degradation under worse case conditions in planar MOSFETs and FinFETs,

HCI qualification – measurement, analysis and modeling

HCI under AC conditions,

Process solutions to reduce HCI: DDD, spacer with LDD implant, HALO/Pockets;

HCI scaling and integration

5 NBTI=Negative-Bias-Temperature-Instability,

Degradation Mechanism and modeling; Interface traps; The Reactive-Diffusion (R-D) degradation model, PBTI;

Stress time and degradation saturation; NBTI recovery; Dynamic NBTI

Qualification and modeling; NBTI Temperature dependency; NBTI Voltage exponential dependency; Voltage/Field acceleration factor

Process dependency; Boron Penetration, ; Oxynitridization, DPN; Fluorine passivation,

6 GOI=Gate Oxide Integrity,

GOX scaling, interfaces, Leakage; Tunneling, TAT, Qbd, Vbd,; Layout sensitivity;

Weibull distribution

Charge inside GOX, C-V;

Vbd; SBD, HBD,

TDDB – physical mechanisms, IBM modeling,

Process Enhancement GOI

Capacitors reliability, with Oxide-Nitride-Oxide, Nitride, Ta2O5; HKMG (Hf-based); TDDB of FinFETs,

TDDB – Qualification and Modeling

IMD-TDDB

7 PID=Plasma Induced Damage,

The mechanism of PID; Plasma non-uniformity, shading

Degradation of dielectric layers during PID

Antenna Ratio: traditional definition; Antenna rules, calculations and examples; Limitation of the traditional ratio; Cumulative plasma damage

PID dependency on integration flow; PID dependency on Gate oxide;

PID stress and measurement methods, PID structures

Protection: bridging, protective diode; Well charging, protection

8 Environmental qualification and the foundry responsibility

Foundry TQV for platform development; SRAM TEG: structure, scaling, operation, layout

Level-2 qualification – Environmental tests

·       Early Life Failure Rate (ELFR) – calculation

·       Burin-In for screening

·       Random failures, x-ray soft error,

·       High-temperature operating life (HTOL)

·       Biased temperature and humidity (THB, 85/85)

·       Temperature cycling (TMCL)

·       Autoclave

9 Qualification; The fabless/foundry reliability and qualification “relationship”,

The foundry TQV for qualification and WLR in HVM;

Reliability characterization; JEDEC JP001 (1, 2, 3)

Examples for foundry physical reliability qual plan and results

Additional qualification needs (PID, DRV, CA, Cp/Cpk)

10 Reliability for Automotive;

IoT, Automotive, connectivity. Examples for different Automotive applications

Different qualification requirements for Automotive;

Reliability for Automotive; Cumulative failure and life-time

The mission profile; AEC-Q100; ZEVI, Environmental qualification and Burn-In

Quality and Manufacturing for Automotive; Risk management; IATF16949; The Zero-defect program’ Process Control for Automotive’ Continuance Improvement plan’ 8D report, Failure Analysis capabilities

DfA – Design-for-Automotive; Devices, rules, Guidelines and DfM’ SPICE modeling – Aging’ IPs, ISO26262’ ASIL, Safety Function’ Trace and tractability

11 ESD=Electrostatics Discharge,

ESD and Triboelectric; The (cost) impact of ESD; The level of voltage build-up, examples for failures,

ESD Prevention and protection,

ESD Modeling; HBM; MM; CDM

ESD Protection; example

 

References:

  • Reliability and Failure of Electronic Materials and Devices, Milton Ohring, Academic Press (1998)
  • Reliability Wearout Mechanisms in Advanced CMOS Technology (IEEE Press Series on Microelectronic Systems, Alvin W. Strong et al., John Wiley (2009)
  • Up to date list of papers.

Expected Results:

Fulfilling course requirements student is expected to be able to:

  1. Understand the different reliability mechanisms in CMOS devices,
  2. Understand the dependencies between the process and the stress conditions in the field on the failure rate
  3. Fully characterize and analyze the reliability performance and figure of merits of different devices, by carful understanding the different mechanisms and the reliability characterization.
  4. Deep understanding of the way the semiconductor devices operates under stress (transistors, capacitors, resistors and more) thus how to optimize them to achieve the needed performance, with emphasize on reliability for automotive

Prerequisites:

  • 044231 Electron Devices 1 (MOS)

Assignments:

The course will consist of: lectures, self-practice exercises (35% of the grade), and a final exam (65% of the grade).

Course schedule:

18-Sep’22 1 09:00 ~ 09:50 Course Introduction,
Introduction to Reliability and time degradation, (TAF, CAF, VAF), modeling
2 10:00 ~ 10:50 Physical failure mechanisms: HCI, NBTI, EM, SM, GOI, ESD, others
3 11:00 ~ 12:00 Electromigration: definition; Mass motion and flux modeling; Blech length; Void formation; Stress effects
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Electromigration – testing and qualification;
6 14:00 ~ 15:15 Electromigration: Grain Size dependency, Alloys, Barrier metals and other process related performances improvement, N7 and N5 BEOL solutions
7 15:30 ~ 17:00 Electromigration: LT as function of Width and length, AC vs DC conditions; EM scaling limitations.
Stress Migration: Introduction
8 17:10 ~ 18:00 Stress Migration: void formation and growth; SIV modeling; Layout solution, double via solution; Stacked via sensitivity, effect of misalignment
19-Sep’22 1 09:00 ~ 09:50 Hot-Carrier-Injection: mechanism and modeling; DAHC (Drain Avalanche Hot carrier), CHE (Channel hot Electron), SHE (Substrate Hot Electron), others; Lucky Electron Model,
2 10:00 ~ 10:50 HCI: HCI degradation under worse case conditions in planar MOSFETs and FinFETs, qualification – measurement, analysis and modeling, Process solutions to reduce HCI: DDD, spacer with LDD implant, HALO/Pockets; Aging
3 11:00 ~ 12:00 Negative-Bias-Temperature-Instability: Degradation Mechanism and modeling; Interface traps; The Reactive-Diffusion (R-D) degradation model, PBTI;
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 NBTI: Stress time and degradation saturation; NBTI recovery; Dynamic NBTI; Qualification and modeling; Process dependency; Boron Penetration, ; Oxynitridization, DPN; Fluorine passivation,
6 14:00 ~ 15:15 Gate Oxide Integrity: GOX scaling, interfaces, Leakage; Tunneling, TAT, Qbd, Vbd,; Layout sensitivity;
7 15:30 ~ 17:00 GOI: Weibull distribution; Charge inside GOX, C-V; TDDB – physical mechanisms, IBM modeling,
8 17:10 ~ 18:00 GOI / Tirgol
20-Sep’22 1 09:00 ~ 09:50 GOI: Process Enhancement GOI; Oxide-Nitride-Oxide, Nitride, Ta2O5; HKMG (Hf-based);
2 10:00 ~ 10:50 GOI:  TDDB of FinFETs, TDDB – Qualification and Modeling, IMD-TDDB
3 11:00 ~ 12:00 Plasma Induced Damage: The mechanism of PID; Plasma non-uniformity, shading, Antenna Ratio: traditional definition; Antenna rules, calculations and examples; Limitation of the traditional ratio; Cumulative plasma damage; Protection: bridging, protective diode; Well charging, protection
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Technology qualification: TEG, TQV, ELFR, Burn-In, HTOL, THB, 85/85
6 14:00 ~ 15:15 Technology qualification: TMCL, JEDEC JP001
7 15:30 ~ 17:00 Automotive: Reliability, AEC-Q100, ZEVI, Mission Profile, Quality, IARF16949, DFA, IPs, ISO 26262
8 17:10 ~ 18:00 Electrostatics Discharge: Mechanism, examples for failures, Prevention and protection, HBM, MM, CDM

 

Lecturer Bio:

Dr. Eitan N. Shauly received the B.Sc. degree in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, in 1989, and M.Sc. and Ph.D. degrees in materials engineering from the Technicon — Institute of Technology, Haifa, in 1995 and 2001, respectively. He has worked for Tower Semiconductor since 1989. During 1989–1994 he was a diffusion and ion implantation engineer. During 1994–1997 he was a device/Integration engineer, focusing on process integration and process modeling. Since 1998 he is doing integration, focusing on platform development, design rules, Design-for-Manufacturing and Automotive. Dr. Shauly is also teaching at the faculty of Material Engineering, Technicon Haifa, courses related to VLSI technology: “VLSI processing” and “CMOS Devices and Integration”.

 

For registration click here 

*Registration is open until August 18, 2022

Michal Kagan

ACRC workshop ENTREPRENEURSHIP IN SEMICONDUCTORS with MICHAEL KAGAN

 

Michael Kagan is NVIDIA CTO (Chief Technology Officer) since May 2020. He joined NVIDIA through Mellanox acquisition.

Michael Kagan was previously Mellanox CTO and a co-founder of Mellanox that was founded in April 1999.

From 1983 to April 1999, Mr. Kagan held a number of architecture and design positions at Intel Corporation. While at Intel Corporation, Mr. Kagan was architect of the i860XP vector processor, managed Pentium MMX design, and managed the architecture team of the Basic PC product group.

Mr. Kagan holds a BSc. in Electrical Engineering from the Technion — Israel Institute of Technology.

Important: registration is required

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https://acrc.net.techniomm wave imaging for automotive and beyond

mm-Wave Imaging for Automotive and Beyond

Millimeter wave frequency operation offers wide bandwidths, precise localization, and rich material interaction and penetration capability.  Meeting consumer demand for enhanced safety, 77GHz automotive radar is one of the fastest growing features in automotive.  Leveraging the dense integration and fast transistor performance of modern silicon processes, emerging MMICs are delivering higher performance in a smaller form factor and are also extending the mm-wave capabilities to other sensing markets.  Radar’s next frontier is to improve angular resolution towards a true imaging radar that can complement or displace lidars in highly automated driving.  This talk will cover these application trends and how they are enabled by emerging radar ICs.

 

Brian Ginsburg received his S.B., M.Eng., and Ph.D. degrees from the Massachusetts Institute of Technology.   He joined Texas Instruments, Dallas, Texas in 2007 working in its wireless business and TI’s Kilby Labs.  Now, he is a Distinguished Member of Technical Staff and the systems manager of TI’s radar business.  He has served on the technical program committee for the International Solid-State Circuits Symposium and is Symposium Chair of the 2022 Symposium on VLSI Technology and Circuits.

 

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Danielle Griffith, Texas Instruments, Dallas, Texas

Towards zero: Power consumption trends in low data rate wireless connectivity products

The low power IoT market began in earnest in 1999 with the launch of the first commercial Bluetooth® device.  Analysis of >200 datasheets and published IEEE conference and journal papers shows that since then, active power consumption for these low data rate radios has reduced by 20x, while sensitivity has improved by 15dB.  Large power reductions have also been seen in metrics such as the standby and BLE-1s connection interval currents.  This talk will explore which innovations have made this possible, and what power consumption trends we can we expect in the future.   Questions to be addressed include:  How does power consumption trade off with data rate, transmit power and receiver sensitivity? How low power is low enough? Where do wakeup radios and energy harvesting fit into this?  Where will it all end?

 

Danielle Griffith received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology, Cambridge.   In 2003, she joined Texas Instruments in Dallas, Texas and is a Fellow in the Connectivity business unit.  Her current focus areas are circuits and architectures for efficient wireless systems, low power oscillators and MEMS circuitry.   She has published a book chapter and >50 papers, most of them in IEEE journals or conferences.   Danielle holds 19 issued US patents and has given numerous university and IEEE conference tutorial and workshop sessions.  She has been a member of the Technical Program Committees for the IEEE RFIC Symposium (2014-2015), IEEE International Solid-State Circuits Conference (2016-2019), and the IEEE VLSI Symposium (2019-2020).  She is a senior member of the IEEE, an associate editor of the IEEE Journal of Solid-State Circuits since 2020, and has been selected as Distinguished Lecturer of the IEEE Solid-State Circuits Society for 2021–2022.

 

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Microelectronic Systems for Improved Quality of Life

Microelectronic Systems for Improved Quality of Life

Microelectronic revolutions come in waves that are driven by necessity. Currently, the aging population is creating a need for various kinds of electronic systems to improve their quality of life. These include the restoration of lost functionality via electronic implants, better health screening technology and non-invasive monitoring in the home environment. This talk presents work that has been done towards addressing these needs, whether it be through the development of new required building blocks or through the development of more complex systems that combine custom built hardware and software. In particular the talk covers work done towards developing a vestibular implant for balance restoration, a single chip low-power imager for a bionic eye, a cancer screening capsule for detecting early-stage carcinomas in the small intestine, a bio-inspired acoustic scene analysis system, the development of the ElectroUteroGraph, as well as the use of custom chips for the design of adaptive metamaterials.

Julius Georgiou (IEEE M’98-SM’08) is an Associate Professor at the University of Cyprus. He received his M.Eng degree in Electrical and Electronic Engineering and Ph.D. degree from Imperial College London in 1998 and 2003 respectively. For two years he worked as Head of Micropower Design in a technology start-up company, Toumaz Technology.  In 2004 he joined the Johns Hopkins University as a Postdoctoral Fellow, before becoming a faculty member at the University of Cyprus from 2005 to date. He is one of the co-founders of AJM Med-i-CAPs Ltd.

Prof. Georgiou is a member of the IEEE Circuits and Systems Society, is the Chair of the IEEE Biomedical and Life Science Circuits and Systems (BioCAS) Technical Committee, as well as a member of the IEEE Circuits and Systems Society Analog Signal Processing Technical Committee. He served as the General Chair of the 2010 IEEE Biomedical Circuits and Systems Conference and is the Action Chair of the EU COST Action ICT-1401 on “Memristors-Devices, Models, Circuits, Systems and Applications – MemoCIS”. Prof. Georgiou was an IEEE Circuits and Systems Society Distinguished Lecturer for 2016-2017. He also was an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems, an Associate Editor of the Frontiers in Neuromorphic Engineering Journal and a Guest Editor for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems, for Programmable Metamaterials and also Circuits and Systems for Smart Agriculture. He is a recipient of a best paper award at the IEEE ISCAS 2011 International Symposium and at the IEEE BioDevices 2008 Conference. In 2016 he received ONE Award from the President of the Republic of Cyprus for his research accomplishments.