Author: rshiraz

Nanoscale Design Methodologies for Low-Power and Robust Gigascale

Supervisor: Prof. Volkan Kursun

Place: Technion

Date: 22.6.08

Abstract:

CIRCUIT DESIGN TECHNIQUES FOR LOW-POWER AND ROBUST NANOSCALE INTEGRATION

DAY, 1 22 June 2008

9:30-11:00    Domino logic and body biasing

11:30-13:00  Multi-Threshold circuits (MTCMOS)

14:00-15:30  Memory circuits

16:00-17:30  Power supply switching and voltage conversion circuits

DAY 2, 23 June 2008

9:30-11:00  Design techniques for variation tolerant circuits

11:30-13:00 Temperature-adaptive circuits

14:00-15:30 Designing with FinFET transistors I

16:00 – 17:30  Designing with FinFET transistors II

Volkan Kursun

Assistant Professor

Biography

Volkan Kursun received the B.S. degree in Electrical and Electronics Engineering from the Middle East Technical University, Ankara, Turkey in 1999, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, New York in 2001 and 2004, respectively.

He performed research on mixed-signal thermal inkjet integrated circuits with Xerox Corporation, Webster, New York in 2000. During summers 2001 and 2002, he was with Intel Microprocessor Research Laboratories, Hillsboro, Oregon, responsible for the modeling and design of high frequency monolithic power supplies. He has been an assistant professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison  since 2004.

His current research interests are in the areas of low voltage, low power, and high performance integrated circuit design, modeling of semiconductor devices, and emerging integrated circuit technologies.

Dr. Kursun is an associate editor of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the IEEE Transactions on Circuits and Systems I, the IEEE Transactions on Circuits and Systems II, and the Journal of Circuits, Systems, and Computers (JCSC) and an organizing / technical program committee member of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), ACM/SIGDA Great Lakes Symposium on VLSI (GLSVLSI), IEEE International Symposium on Circuits and Systems (ISCAS), IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), and the IEEE/ACM International Symposium on Quality Electronic Design (ISQED).

 

Contact:

Phone: 608-262-8804

Fax: 608-262-8804

E-mail: kursun@engr.wisc

Mixed-Signal Circuit and Architecture Design for CMOS Data Converters

Supervisor: Prof. Murmann

Place: Technion

Date: 28-12-08

Abstract: 

Dates: 28-30 December 2008
Location: Meyer building, Department of electrical engineering, Technion, Haifa, Israel
This course will cover the design of mixed-signal integrated circuits for implementing the interfaces between analog and digital signals in CMOS VLSI systems. Topics include fundamental circuit elements such as comparators, track-and-hold circuits, and operational transconductance amplifiers. Architecture-specific material will focus on pipeline ADCs and current-steering DACs. The course ends with a discussion on technological limits and current research topics.
 
Sunday:
08:30-10:00, 10:30-12:00 Data converter architectures, specifications and trends; voltage comparator design
13:30-15:00, 15:30-17:00. Track-and-hold circuit design, analysis of nonidealities such as noise and distortion
Monday:
08:30-10:00, 10:30-12:00 Operational transconductance amplifiers, gm/ID based design
13:30-15:00, 15:30-17:00 Pipeline ADCs, architecture and circuit design
Tuesday
08:30-10:00, 10:30-12:00 Fundamentals of Nyquist DAC design; data converter testing
13:30-15:00, 15:30-17:00 Limits on ADC power dissipation; research topics
  
Prof. Boris Murmann, Stanford University
Short biography
Boris Murmann received the Dipl.-Ing. (FH) degree in communications engineering from Fachhochschule Dieburg, Germany, in 1994, and the M.S. degree in electrical engineering from Santa Clara University, Santa Clara, CA, in 1999. In 2003, he received the Ph.D. degree in electrical engineering from the University of California at Berkeley.
From 1994 to 1997, he was with Neutron Mikrolektronik GmbH, Hanau, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. During 2001 and 2002, he held summer positions with the High-Speed Converter Group at Analog Devices, Wilmington, MA. Since 2004, he has been an Assistant Professor in the Department of Electrical Engineering, Stanford, CA. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces.
At UC Berkeley, Dr. Murmann received the outstanding graduate student instructor award in 1999 and the CalView award for excellence in distance education in 2003. He was a co-recipient of the Meritorious Paper Award at the 2005 US Government Microcircuit & Critical Technology Conference. Dr. Murmann served as a guest editor for the EURASIP Journal on Advances in Signal Processing in 2007. He currently serves as a member of the International Solid-State-Circuits Conference (ISSCC) program committee.

Course Material

 

Low Power CMOS Circuit Design

Supervisor: Professor Yusuf Leblebici

Place: Auditorium Floor 10, Electrical Engineering Building, Technion

Date: 12-14 October 2009

Abstract: 

Seminar “Low Power CMOS Circuit Design”

12-14 October 2009

Professor Yusuf Leblebici

Yusuf Leblebici received the B.S. and M.S. degrees in electrical engineering from Istanbul Technical University in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990.

 

Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI), where he established and directed the VLSI Design Laboratory, and also served as a project director at the New England Center for Analog and Mixed-Signal IC Design. He also worked as the Microelectronics Program Coordinator at Sabanci University. Since January 2002, he has been a full professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of the Microelectronic Systems Laboratory. His research interests include design of high-speed and low-power CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, modeling and simulation of nano-electronic circuits, intelligent sensor interfaces, and VLSI reliability analysis. Dr. Leblebici is the coauthor of three textbooks, namely, “CMOS Digital Integrated Circuits: Analysis and Design” (McGraw Hill, 1996, 1999 and 2003), “Hot-Carrier Reliability of MOS VLSI Circuits” (Kluwer Academic, 1993), “CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications” (Springer, 2007) as well as more than 150 scientific articles published in international journals and conferences.

 

Dr. Leblebici has served on the organizing and technical program committees of the 1995 European Conference on Circuit Theory and Design (ECCTD 1995), the 2004 European Workshop on Microelectronics Education (EWME 2004), and as General Co-Chair of the Joint 2006 European Solid-State Circuits Conference and European Solid-State Device Research Conference (ESSCIRC-ESSDERC 2006). He also served as an Associate Editor of IEEE Transactions on Circuits and Systems II, and as an Associate Editor of IEEE Transactions on VLSI. He received the Young Scientist Award of the Turkish Scientific and Technological Research Councils in 1995, and the Joseph Samuel Satin Distinguished Fellow Award of the Worcester Polytechnic Institute in 1999.

 

Syllabus

Low Power CMOS Circuit Design

  1. Introduction to low power CMOS circuit design
    2. Dynamic (switching) and leakage power consumption
    3. Influence of technology scaling and nanometer CMOS
    4. Minimizing energy consumption under performance constraints
    5. Dynamic voltage-frequency scaling (DVFS) techniques
    6. Physics and modeling of subthreshold operation in MOSFETs
    7. CMOS logic operating in subthreshold regime
    8. Benefits and limitations of subthreshold operation in view
    of increased leakage in nanometer CMOS technologies
    9. Current mode operation for low power
    10. Subthreshold source-coupled logic (STSCL) circuits
    11. Complex logic gates using STSCL style
    12. Two-phase pipelining to improve activity rate
    13. Source-follower buffer drivers for large fanout
    14. Design automation for standard-cell based STSCL design
    15. Cell library creation, placement & routing techniques

 

Agenda

 

Monday 12.10.09

 

13:00 – 13:30 Registration

13:30 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 18:00 lecture

 

Tuesday 13.10.09

 

08:30 – 09:00 Coffee

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

 

Wednesday, 14.10.09

 

08:30 – 09:00 Coffee

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

 

Admission

Admission to the course is free of charge only to Members of the ACRC,

Brief RFIC seminar

Supervisor: Prof. Avinoam Kolodny

Place: Auditorium Floor 10, Electrical Engineering Building, Technion

Date: 25.1.10

Abstract:

Brief RFIC seminar

25.1.10

Floor 10, Room1007 Electrical Engineering Building, Technion

 

 

13:30 – 13:45 Reception & Light Refreshments

 

14:00 – 14:30 Dr. Christopher D. Hull

RF transceiver from 3.x towards 4G/ OFDM based systems

 

14:30 – 15:00 Dr. Ofir Degani

Past present and future CMOS Power amplifiers for Wireless

Communications

 

15:00 – 15:30 Coffee Break

 

15:30 – 16:00 Mr. Emanuel Cohen

60 GHz system and components in CMOS for low power compact

Phase Array applications Open discussion- 30 min

 

16:00 – 16:30 Discussion

 

Power Supply Issues in VLSI Systems

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 18.7.10

Abstract:

ACRC Workshop on Challenges and Recent Research in On-Chip Power Delivery

July 18, 2010
Technion, EE building, Auditorium 1003 (10th floor)

Goals: The core issues in on-chip power delivery will be discussed, and related research problems outlined. Some examples of specific research results in the area of on-chip DC-DC conversion and algorithms for efficient IR drop analysis will also be described.
Participants: Engineers from ACRC companies, graduate students and researchers engaged in various aspects of power supply subsystems (e.g. voltage conversion, regulation, on-chip power delivery, power management).

Agenda:
09:30 – 10:00   Registration and refreshments
10:00 – 10:45   Prof. Eby Friedman (Technion)
Introduction/Tutorial: Challenges of Power Delivery
in VLSI Systems.
10:45 – 11:15   Dr. Michael Zelikson (Intel)
System-on-Chip Power Delivery Management – Goals,
Trends and Issues.
The main principles of a modern power delivery
system, possible development directions, anticipated
challenges and interes/files/2018/06/Challenges-of-Integrated-Systems-Power-Delivery-Management_-back.pdfting research directions.
Integrated Circuit Power Management Platforms incorporate
logic and analog blocks together with high voltage and
current power drivers on the same chip. This combination
allows serving a host of applications ranging from power
management in portable devices, power delivery in computer
motherboards through dc dc motor drives and to LED drivers
in street lighting and TV screens.
12:00 – 12:30   Eitan Rosen (Marvell)
Local and Global Investigation of On-chip Power
Simulations of Local and Global Power issues enable understanding
of issues and Power grid and de-coupling capacitors methodology
development.

12:30 – 13:00  Nimrod Ben Ari (Zoran)
 Zoran On-chip Distributed Power Switch
Zoran Power Switch methodology and implementation, including
supporting peripheral circuits, And silicon results.

13:00 – 13: 30   Lunch Break

13:30 – 14:00   Gregory Sizikov (Intel)
Efficiency Considerations for On-chip DC-DC Buck Converters
An analytic method to evaluate frequency dependent losses in on-chip
DC-DC buck converters will be described. The analytical model will
be used for optimizing switching frequency and for minimizing losses
at light and heavy loads.

14:00 – 14:30   Dr. Aharon Unikovsky (Tower)
 A bandgap reference circuit for wide voltage range applications
A bandgap circuit that works in a voltage range of 4V up to 42V
with a very low current consumption and high PSRR.

14:30 – 14:45   Coffee Break

15:00 – 16:00    Panel/Brainstorming session: Open research problems and development directions in VLSI power supply management

16:00 – 16:15   Conclusion

You are invited to a guest lecture after the seminar:
16:30-17:30 Dr.Ingmar Kallfass
The use and benefit of modern active millimeter-wave monolithic integrated circuit (MMIC) technology in high resolution sensing, imaging and high data rate wireless communication applications will be discussed. State-of-the-art in millimeter-wave low-noise and solid-state power amplification is briefly covered. Examples of MMICs based on state-of-the-art metamorphic high electron mobility transistor (mHEMT) technology with gate lengths down to 35 nm and cutoff frequencies fT of over 500 GHz and fmax of more than 700 GHz will be presented. A focus is on the multifunctional integration of analog frontend receivers and transmitters as well as frequency multipliers covering the entire millimeter-wave range up to and beyond 300 GHz. Furthermore, an ongoing Technion – Fraunhofer cooperation in the field of high-speed analog-to-digital converters based on InP hetero-bipolar transistor technology is introduced.

Variation and Low Voltage Digital Circuit Design

Supervisor: Professor David Harris

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 30.12.10

Abstract:

Variation and Low Voltage Digital Circuit Design

Professor David  Harris

  Dep. of Engineering Harvey Mudd College in Claremont, CA.

30.12.10

Auditorium floor 10

This course addresses the challenges of nanometer circuit design arising from variation and low-voltage operation.  The course begins with a review of the sources of variation and the impact on delay, energy, and functionality.  It examines back-of-the envelope statistical analysis techniques to rapidly assess the impact of variation.  Variation effects are accentuated for circuits running at low voltage, particularly in applications such as embedded sensing and dynamic voltage scaling where energy efficiency is critical.  The course describes methods and limits of low-voltage circuit design, including combinational logic, registers, and SRAM design.  Resilient sequencing elements such as Razor and DSTB are particularly interesting because they can reduce the guard bands required to accommodate variation in DVS systems.

 

David  Harris is a Professor of Engineering at Harvey Mudd College in

Claremont, CA.  Prof. Harris received his Ph.D. from Stanford University and his S.B. and M.Eng. degrees from MIT. He has designed circuits at Intel, Hewlett-Packard, Sun Microsystems, and elsewhere.

His research interests include high-performance and low-power digital circuit design, arithmetic, and microprocessors.  Prof. Harris is the co-author of CMOS VLSI Design, Logical Effort, and two other books in the field.

Agenda

08:30 – 09:00 Registration

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

The seminar is free of charge to ACRC members, Intel, Zoran, Marvell, Mellanox.

Others will be charged 500 Shekels+VAT for participating in the seminar.

Course Material

Analog and Mixed-signal Integrated Circuit Design

Supervisor: Prof. Zeljko Ignjatovic

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 15.2.11

Abstract:

Analog and Mixed-signal Integrated Circuit Design

Can we describe analog and mixed-signal circuits as telecommunication channels and determine fundamental limits utilizing Information theory tools?

Professor Zeljko Ignjatovic, University of Rochester

15-17.2.11

Technion, EE building, Auditorium 1003 (10th floor)

Academic organizers:  Prof. Eby Friedman and Prof. Avinoam Kolodny

Please, Register Online!

Course description and material: This course will discuss the circuitry, algorithms and architectures used in analog and mixed-signal mode CMOS integrated circuits, provide practical considerations and detailed design examples . In addition, information theoretical concepts closely related to the design of A/D converters will be discussed and their fundamental resolution-bandwidth limits will be presented. The discussion of the following topics is planned:

Agenda

February 15th

 

08:30 – 09:00 Registration

09:00 – 10:30 Introduction to Switched Capacitor (SC) Circuits and basic building blocks

10:30 – 10:45 Coffee Break

10:45 – 13:00 First order and biquad SC filters

13:00 – 14:00 Lunch Break

14:00 – 15:30 High-order SC filters and Non-ideal effects

15:30 – 15:45 Coffee Break

15:45 – 17:00 Other SC stages and Introduction to Sigma-delta A/D converters

February 16th

 

09:00 – 10:30 Noise shaping, MASH structurs and Non-ideal effects

10:30 – 10:45 Coffee Break

10:45 – 13:00 Higher order Sigma-delta Topologies

13:00 – 14:00 Lunch Break

14:00 – 15:30 Spread-spectrum Technique in Sigma-delta ADC

15:30 – 15:45 Coffee Break

15:45 – 17:00 Noise in SC circuits and Sigma-delta ADC; Turbo-code A/D converters

February 17th

 

09:00 – 10:30 CMOS Image Sensors

10:30 – 10:45 Coffee Break

10:45 – 13:00 Pixel designs in CMOS image sensors

13:00 – 14:00 Lunch Break

14:00 – 15:30 Image sensor readout methods with global feedback – improving readout speed and noise

15:30 – 15:45 Coffee Break

15:45 – 17:00 Fully digital image sensors utilizing pixel level Sigma-delta A/D converters

 

The seminar is free of charge to ACRC members, Intel, Marvell, Mellanox, Samsung, Zoran.

Others will be charged 1500 Shekels+VAT for participating in the seminar.

The course is open free of charge for EE students (undergraduate and graduate).

3-dimensional integration of VLSI circuits – technical, challenges and opportunities

Supervisor: Prof. Eby Friedman

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 24.2.11

Abstract: 

You are kindly invited to a Workshop on :

3-dimensional integration of VLSI circuits – technical,  challenges and opportunities

Thursday, 24 Feb 2011, 14:30-17:30

Auditorium Floor 10

 

 

14:15 – 14:30 Registration & Light Refreshments
14:30 – 15:10 Recent Research in 3-D Circuit Design and Related Test Circuits
Prof. Eby G. Friedman, University of Rochester, NY, USA
15:10 – 15:50 Variability Issues in 3-D Clock Distribution Networks
Prof. Vasilis Pavlidis, EPFL, Switzerland
15:50 – 16:10 Coffee Break
16:10 – 16:50 Design and Modeling Methodology of Vertical Interconnects (TSV, mC4…) for 3DI technologies in IBM
Dr. David Goren, IBM, Israel
16:50 – 17:30 Cost Effectiveness of 3D Integration Options
Prof. Dimitrios Velenis, IMEC, Belgium

Design considerations and basic analysis for Inductors and CMOS Radio Frequency Integrated Circuits

Supervisor: Dror Regev

Place: Technion, EE building, Room 1061 (10th floor)

Date: 3.5.11

Abstract:

Design considerations and basic analysis for Inductors and CMOS Radio Frequency Integrated Circuits

Mr. Dror Regev – Terra Freedom Consulting
Dates: May 3,4 2011

Location: Meyer building, Auditorium floor 10

Department of electrical engineering, Technion, Haifa, Israel

This course will start with the design considerations and performance of RFIC inductors and continue with principles, strategies, topologies and challenges in basic CMOS RF circuit design. Simple but powerful analytical tools will be presented to allow designers a better understanding of the challenges and tradeoffs in circuit design preceding CAD circuit simulations. Approaches and tools employed in the seminar may be used as a basis for advanced analysis and design of other RFIC circuits.

Tusday, 3rd of May

08:30-10:00 RFIC Inductors – Inductance basics in Coax, Microstrip and Coupled Micro strips. Layout considerations for Spiral Inductors, Inductor Parasitic, simplified model and Quality factor analysis. Effect of ground and Si substrate on Inductor performance.
10:30-12:00, 13:30-15:00, 15:30-17:00 LNA’s – Common Source Simultaneous Noise and Impedance Matching. Voltage gain analysis of a CS LNA at frequency domain. Electrical stability analysis of a CS LNA and related Impedances. Miller Effect in CS and Cascode transistor introduction. Cascode transistor stability issues. CS IIP3 optimization through gate biasing and the effect of degeneration inductance feedback.

Wednesday, 4th of May

08:30-10:00 Class A PA – maximum linear output power and related optimal load, gain vs. max power out load, device size and operating point considerations, effect of transistor and circuit parasitic, PA stability and stabilization through feedback.
10:30-12:00 Passive Mixer – Modulator in Frequency domain, Time domain analysis, device and operation point optimization, Balanced mixers.
13:30-15:00 Active Mixer – Active design approach and considerations, voltage gain, noise considerations and linearity.
15:30-17:00 VCO-Phase noise and its implications, Oscillator harmonics, Oscillator tanks and oscillation frequency, Tank quality factor and related second order phase noise, Tank design. Methods for injecting energy into the tank, Colpitts Oscillator and it’s phase noise, Colpitts evolution to differential design, VCO Biasing, Large signal analysis, complementary design vs. NMOS design.

Mr. Dror Regev
Short biography

Dror Regev received the BsC degree in electrical engineering from Ben-Gurion University, Israel, in 1987, and the MsC. degree in management from Boston University, in 1994. He is currently teaching CMOS RFIC Circuit Design as an invited lecturer in the Department of Electrical and Computer Engineering, Ben-Gurion University, Israel. From 2006 he teaches RFIC design classes he authored to engineers in the Israeli wireless industry. He is member of IEEE Solid-State Circuits Society.
In 2007, he established an RFIC consulting firm and focused for 3 years on starting up Elipse RFIC Array Devices the first Israeli RFIC design house in Kfar Neter, Israel.
Prior to that, Mr. Regev was with Tower Semiconductors, Israel; Acer Labs, San Jose CA; Intel Haifa, Intel Kiriat Gat; Sierra Microwave Technology, Austin Texas and Elta systems, Israel in senior R&D and Engineering management positions.

The seminar is free of charge to ACRC members, Intel, Marvell, Mellanox, Samsung, Zoran.

Others will be charged 1000 Shekels+VAT for participating in the seminar.

The seminar is open free of charge for EE students (undergraduate and graduate).