Kamran Eshraghian Seminar

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE Fischbach building, Floor 10 Auditorium 1003

Date: 16.6.11


Program: Addressing Technologies Beyond Moore’s Law: the reality of nanoscale devices as part of future System on System Integration

Speaker: Prof. Kamran Eshraghian

Date: 16.6.11

Location: Electrical Engineering Building, Floor 10 Auditorium 1003

Department of Electrical Engineering, Technion, Haifa, Israel

Synopsys: The evolution of SoC (System-on-Chip) and SiP (System-in-Package) introduce a 3rd dimension (3D) that maybe described in terms of a “Volumetric Growth Law” that takes into account the multitechnology nature of integration for a future whereby hyperintegration becomes the new innovation domain. This new frontier is conjectured to move us way beyond Gordon Moore’s 2-D scaling relationship as we begin to uncover new relationships and principles. While the future is becoming more difficult to predict, most likely we could anticipate an accelerating pace of change that span health sciences and intelligent health care, environmental management, smart energy management through to new innovations in man-machine interfaces, processing and communications. This seminar will explore the integration and likely convergence of disparate and significantly different and challenging technologies that are gaining more focus in the quest for a new processing/computing paradigm. The presentation will highlight the inevitability of 3D hyperintegration using technologies that are either in their infancy or those yet to be uncovered through initiatives of material physicists, computational chemists, and bioengineers and will focus upon one such technology such as Memristor, the 4th electronic component conjectured to challenge the perspective and the mind-set that researchers and industry currently may have.


Morning session 09.00 – 12.00

lunch break,

Afternoon session 13.00 – 15.00

Topics to be covered:

  1. From humble electron to System-on-System (SoS) Integrated domain
  2. Moore’s Law limitations?
  3. Multilayered technology design space
  4. Active substrates
  5. Insert substrate
  6. Multitechnology road map – future product-line inspired by innovations
  7. Disruptive technologies – an introduction to:
  8. Single electron transistor (SET)
  9. Carbon nano tube FET (CNFET)

iii.     Nano-scale nonlinear photonic circuits

  1. Metamaterial domain – negative index materials
  2. Subwavelength nanoparticles
  3. Nanocircuit elements at optical frequencies
  4. RLC based filters – how do they behave
  5. Future of Universal Memory
  6. Evolution of nonvolatile resistive switching memory technologies

vii.     Memristor (memory resistors) – the 4th fundamental circuit element

  1. 3-Dimentional hyperintegration
  2. System-on-Chip (SoC) and System-on-System (SoS) Integration
  3. Non-Moore’s integration
  4. System-on-System (SoS) design space
  5. Multitechnology platform
  6. Volumetric thresholding
  7. Applications
  8. Memristor-based Circuits and System Architectures
  9. Principles of operation and fundamentals
  10. Processing technology
  11. Modeling and design concepts
  12. Characterization and Modeling behavior
  13. Simple model

iii.     More complex models

  1. Memristor-MOS based circuits
  2. Applications

Kamran Eshraghian is best known in international arena as being one of the fathers of CMOS VLSI (Very Large Scale Integration) having influenced two generations of researchers in both academia and industry in silicon based circuits and systems. He obtained his PhD, MEngSc, and BTech, degrees from the University of Adelaide, South Australia and Dr.-Ing e.h., from the University of Ulm, Germany. In 1979, he joined the Department of Electrical and Electronic Engineering at the University of Adelaide, South Australia, after spending some ten years with Philips Research, both in Europe and Australia. In 1994, he was invited to take up the Foundation Chair of Computer, Electronics and Communications Engineering in Western Australia, and became the Head of School of Engineering and Mathematics and Distinguished University Professor and subsequently became the Director of Electron Science Research Institute. In 2004, he became Founder/President of Elabs as part of his vision for horizontal integration of nanolectronics with those of photo-based systems, thus creating a new design domain for system on

Professor Andrea Baschirotto

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE Fischbach building, Floor 10 Auditorium 1003

Date: 6-8.9.11


A short intensive course on

Low-Voltage Analog CMOS Design

in scaled CMOS technology Circuit

Prof. Andrea Baschirotto, Milan-Bicocca University



Dates: 6-8 September 2011

Location:  Department of electrical engineering, Auditorium floor 10

Technion, Haifa, Israel

This course will cover the design of mixed-signal integrated circuits to be implemented in scaled CMOS technology, i.e. with device size smaller than 90nm.

The course will start with the description of MOS transistor behavior in scaled technologies, showing that analog performance metrics are typically worse than in longer minimum-size process. Nonetheless, the course will show circuit and system solutions enabling the design of high performance devices in scaled technologies.

08:30-10:00, 10:30-12:00 Basic CMOS operation, CMOS technology scaling trends
13:30-15:00, 15:30-17:00 CMOS technology scaling trends (cont.), Low voltage (LV) operation – LV at transistor  Level

08:30-10:00, 10:30-12:00LV at circuit level (Opamp design, Basic bandgap design)

13:30-15:00, 15:30-17:00LV at system level (Analog CT filters)


08:30-10:00, 10:30-12:00LV at system level (Analog CT filters – cont., SC circuits)

13:30-15:00, 15:30-17:00 LV at system level (A/D Converters)

  The seminar is free of charge to ACRC members, Intel, Marvell, Mellanox,  Zoran.Others will be charged 1500 Shekels+VAT for participating in the seminar.

The seminar is open free of charge for EE students (undergraduate and graduate).





 Prof. Andrea Baschirotto, Milan-Bicocca University


Short biography


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Andrea Baschirotto graduated in Electronic Engineering (summa cum laude) from the University of Pavia in 1989. In 1994, he received the Ph.D. degree in electronics engineering from the University of Pavia.

In 1994, he joined the Department of Electronics, University of Pavia, as a Researcher (Assistant Professor).

In 1998, he joined the Department of Innovation Engineering, University of Lecce, Italy, as an Associate Professor.

In 2007, he joined the Department of Physics, University of Milan-Bicocca, Italy, as an Associate Professor.

Andrea Baschirotto has a long-term experience in microelectronics for what concerns teaching, researching, and industrial designing.

He is teaching regular Academic courses since 1997. He organized the full educational courses for Electronics Engineering (Bachelor, Master, and Ph.D.) at University of Lecce. He uses to give industrial courses since 1996 (in Bosch, STMicroelectronics, ITC-IRST, Conexant, Mikron, etc…). He is a speaker at the MEAD Summer courses held at EPFL (Lausanne – Switzerland). He uses to give short courses or tutorial at the most important conferences (ISSCC, ISCAS, PRIME).

About his research activity, he founded and he is leading the Microelectronics Group at University of Lecce, which is collaborating with several companies and research institutions (IMEC, Infineon, University of Pavia, RFDomus, STMicroelectronics, etc….). His main research interests are in the design of CMOS mixed analog/digital integrated circuits, in particular for low-power and/or high-speed signal processing. He participated to several research collaborations, also funded by National and European projects. He is/has been responsible of some National and Regional projects for the design of ASIC. Since 1989, he also personally collaborated with several companies on the design of mixed signals ASICs, like STMicroelectronics, Mikron, ACCO, ITC-IRST, RFDomus (now GloNav), Conexant, etc….

He has authored or co-authored more than 190 papers in international journals and presentations at international conferences, 6 book chapters, and holds 25 USA patents. In addition, he has co-authored more than 120 papers within research collaborations on high-energy physics experiments.

Andrea Baschirotto was Associate Editor IEEE Trans. Circuits Syst. – Part II for the period 2000-2003, and he is now serving IEEE Trans. Circuits Syst. – Part I as an Associate Editor. He has been the Technical Program Committee Chairman for ESSCIRC 2002 and he was the Guest Editor for the IEEE JSSC for ESSCIRC 2003 and ESSCIRC2007. He was the General Chair of IEEE-PRIME2006 and AACD2008.

He is the member of the Technical Program Committee of several international conferences (ISSCC, ESSCIRC, DATE, etc..). He is serving since several years the ESSCIRC TPC as Data Converter Subcommittee Chairman. He has been the secretary of the European Committee of ISSCC Technical Program Committee. He is an IEEE Senior member. He is the founder and the Chairman of the IEEE Solid-State Circuit Society Italian Chapter.

Zvi Or-Bach

Supervisor: Prof Yitzhak Birk

Place: room 861 Electrical Eng. Building

Date: 21.11.2011


Guest Lecture

You are invited to attend a lecture by

Zvi Or-Bach

President and CEO of MonolithingIC 3d



Monolithic 3D – The effective alternative to Dimensional Scaling




The accelerating complexity and cost of dimensional scaling has given birth to “More than Moore”, of which 3D IC is

one of the leading drivers. Recent breakthroughs have added the option of practical monolithic 3D with a 10,000x

higher vertical connectivity. Multiple researchers have reported the potential of 3D IC with rich vertical connectivity to

provide significant average wire length reduction. In fact, some forecast that each device folding could be equivalent to

one process node of dimensional scaling.

We will present several 3D IC flows with their pros and cons, and the future implications.

We will also present how the technology could be apply to related application including:

Memories, Image sensor, Micro-Display and Wafer-Scale-Integration


The lecture will take place on Monday, 21/11/2011

at 10:30-11:30  in room 861

Electrical Eng. Building

Technion City

Advanced CMOS Analog Integrated Circuit Design Course

Supervisor: Prof. Boris Murmann

Place: Meyer Building, Electrical Engineering Department,Technion

Date: 01.03.2012


Advanced CMOS Analog Integrated Circuit Design Course

March 1-9, 2012

Room 165, Meyer building, Electrical Engineering Dept. Technion


This course provides an introduction to the design of analog integrated circuits in advanced CMOS technologies. The course material combines the analytical treatment and practical design of important circuit blocks with short-channel transistors. Specifically, the student will work toward the design of operational transconductance amplifiers (OTAs) for use in switched-capacitor circuits. Important aspects that will be covered on this route are the gm/ID-based compact modeling in support of systematic design, the treatment of electronic noise, and feedback circuit analysis using the return ratio method.

This course is ideal for students who have already completed the “Linear Electronic Circuits” course at the Technion and wish to deepen their understanding toward advanced design. It will be equally compelling for practitioners in industry who are looking for ways to reposition, further or deepen their careers toward cutting-edge analog IC design.


Instructor: Prof. Boris Murmann, Stanford University
Prerequisite: Linear Electronic Circuits http://eecourses.technion.ac.il/044142/ (or equivalent). Knowledge of basic linear system theory, poles and zeros; feedback, basic bipolar and MOS device physics; basic large- and small-signal transistor models.
Required Text: Analysis and Design of Analog Integrated Circuits, 4th Edition, Gray, Hurst, Lewis and Meyer, Wiley, 2001.
Lecture: 28 hours (in English)
Workshops: 10 hours
Circuit Simulation:

Admission :




The course is free of charge to ACRC members, Intel, Marvell, Mellanox and Zoran.

Non-ACRC members  will be charged 2000 Shekels+VAT.


Certificate of accomplishment to be awarded at the completion of the course, passing the final exam and attending all the lectures.



Course Schedule

Date Topic
Thu, March 1, 2012

16:00-17:30 workshop

Lecture Day 1

·        Introduction

·        Review of Square Law MOS Model

·        Short Channel Effects

·        Technology Characterization: gm/ID, fT

·        gm/ID-Based Design

Fri, March 2, 2012
Lecture Day 2

·        Miller Approximation

·        ZVTC Analysis

·        Electronic Noise

Sun, March 4, 2012

15:00-17:00 workshop

Lecture Day 3

·        Review of Common Gate and Common Drain Stages

·        Differential Pair

·        Current Mirrors

·        Process Variations

·        Mismatch


Mon, March 5, 2012

15:00-17:00 workshop

Lecture Day 4

·        Feedback Circuit Analysis using Return Ratio

·        Stability of Feedback Circuits

·        Fully Differential Circuits

·        Introduction to Switched-Capacitor Circuits

·        Analysis and Design of Operational Transconductance Amplifiers

o   Frequency Compensation

o   Step Response


Tue, March 6, 2012

16:00-17:30 workshop

Lecture Day 5

·        Design for low noise

·        Analysis and Design of Operational Transconductance Amplifiers

o   OTA Variants

o   Systematic design

·        Supply Insensitive Biasing

·        Bandgap References


Fri, March 16, 2012 Final Exam


The course is free of charge to EE students (undergraduate and graduate) and has a value of two academic credits

Undergraduate students please register at: http://ug.technion.ac.il/

Graduate students please contact Mrs Keren Seker-Gafni at: kerensg@ee.technion.ac.il

For further information please contact Mrs Suzie Eid: suzie@ef.technion.ac.il


Please note that there are a limited number of  places available on this course. Registration  does not guarantee you a place in the class.

Memristors and Resistive Memory: Devices and Applications

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE building, Auditorium 280 (2nd floor)

Date: 07.03.2012


IEEE/ ACRC Workshop


Memristors and Resistive Memory Devices and Applications in Computer Architecture and Brain-Inspired Systems

Wednesday, March 7, 2012

Technion, EE building, Auditorium 280 (2nd floor)

Goal: Novel devices, based on reversible changes in electrical resistance, are emerging as potential solutions to problems in digital electronica. These devices also hold promise as key elements in future brain-like hardware systems.The goal of this workshop is to introduce researchers and developers from diverse communities (physics, engineering, brain research, industry) to this new field.

Please Register Online!



09:00 – 09:30 Registration and refreshments



09:30 – 10:35 Session 1: Opening and Keynote
Session Chair Prof. Avinoam Kolodny
  Welcome and opening remarks Prof. Adam Shwartz (Technion)
  Keynote: Memristors and Their Applications to Nanocomputing For the Presentation Please Click Here Prof. Sung-Mo “Steve” Kang (University of California)
10:35- 10:45 Break
10:045 – 12:00 Session 2 : Material Properties and Device Physics Session Chair Prof. Joseph Salzman
  Devices based on Mixed Ionic Electronic Condutors (MIEC)

For the Presentation Please Click Here



Prof. Ilan Riess

  Resistive Switching Probed by a Metal-Insulator- Semiconductor Bipolar Transistor For the Presentation Please Click Here Eilam Yalon
  PhaseChange Memory For the Presentation Please Click Here Dr. Nuriel Amir


12:00 – 13:15 Session 3: Circuits Session Chair Prof. Ran Ginosar
  Resistive Memories Promising for Industrial Applications

For the Presentation Please Click Here
Dr. Yakov Roizin

(Tower Semiconductor)


  Spin Torque MTJ-Based Circuits for VLSI Applications

For the Presentation Please Click Here
Prof. Eby Friedman, coauthor Ravi Patel
(U. Rochester)


  Memristor-based Logic Circuit Design

For the Presentation Please Click Here
Shahar Kvatinsky


13:15 – 14:00   Lunch break
14:00 – 15:30 Session 4 :Applications in Brain-Inspired Systems
Session Chair Prof. Ron Meir
  Some architecture inspirations from the biological brain

For the Presentation Please Click Here
Prof. Naftali (Tali) Tishby
(Hebrew University)

  Applying Memristors: Lessons from Biology

For the Presentation Please Click Here
Prof. Shimon Marom



  Influence of memristor synapses on neuron-to-neuron interactions

For the Presentation Please Click Here Dr. Alon Ascoli
(Polotecnico di Torino)
Brain Inspired Computing For the Presentation Please Click Here Dr. Rafi Gidron
(Israel Brain Technology)

15:30 – 15: 45 Coffee Break


15:45 – 17:00 Session 5: Applications in Computer Architecture Session Chair Prof. Isaac keslassy
  Emerging Memory Technologies: Applications For the Presentation Please Click Here Avi Klein (Sandisk)
  Memory Intensive Architectures

For the Presentation Please Click Here
Prof. Uri Weiser



On-Chip Power Delivery and Power Management

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE building, Auditorium 1003 (10th floor)




ACRC Workshop on:
On-Chip Power Delivery and Power Management
Thursday, May 2, 2013
Auditorium 1003, 10th floor, Meyer Building, Electrical Engineering Department
13:30 – 13:50       Registration and Refreshments
13:50 – 14:00      Welcoming notes
14:00 – 14:30      Energy Efficient Clustering of On-Chip Power Delivery System
                               Inna Vaisband (U. of Rochester)
14:30 – 15:00      Multi-supply voltage Dual Mode Logic

                              Alex Fish (Bar-Ilan University)

15:00 – 15:20      Modern CPU Power Management: Challenges & Directions

                              Nir Rosenzweig and Efi Rotem (Intel)

15:20- 15:50      Real Time Power Delivery Management through SW-HW Simbiosis

                              Michael Zelikson  (Intel)
15:50 – 16:05     Coffee Break
                              Shye Shapira (Tower)
16:35 – 17:05      Eye Opening by Ultra Low Power design
                              Tuvia Liran (Nano Retina Inc)
      Eby Friedman (U. of Rochester)