ACRC Course: High-Speed DSP/DAC/ADC-Based Wireline Transceivers

Instructor: Prof. Samuel Palermo, Texas A&M University
Teaching Assistant: TBD
Lectures: 3 days
Academic Points: 1
Exam: TBD
Course Fees: 1700$ (See membership options)

For registration, click here

Registration closes on February 26th, 2026

Date: March 8 – 10, 2025

Time: 9:00 – 18:00 Israel Time

Bio:

Samuel Palermo (S’98-M’07-SM’17) received the B.S. and M.S. degrees in electrical engineering from Texas A&M University, College Station, TX in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA in 2007. From 1999 to 2000, he was with Texas Instruments, Dallas, TX, where he worked on the design of mixed-signal integrated circuits for high-speed serial data communication. From 2006 to 2008, he was with Intel Corporation, Hillsboro, OR, where he worked on high-speed optical and electrical I/O architectures. In 2009, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently the J. W. Runyon Jr. Professor. His research interests include high-speed electrical and optical interconnect architectures, RF photonics, radiation-hardened electronics, and AI computing hardware. He is currently an associate editor for IEEE Journal of Solid-State Circuits and has previously served in this role for IEEE Solid-State Circuits Letters and IEEE Transactions on Circuits and System – II. He has also previously served as a distinguished lecturer for the IEEE Solid-State Circuits Society and on the IEEE CASS Board of Governors.

Course Content

Syllabus:

This course covers system and circuit design techniques of high-speed SERDES transceivers based on DSP, DAC, and ADC blocks. Topics include wireline channels, communication techniques, transmitters, receivers, high-speed digital-to-analog and analog-to-digital converters, equalizers, and clocking circuitry. This course is intended for Analog/Mixed-Signal IC designers and graduate students interested in learning design techniques for state-of-the-art SERDES transceivers used in datacenters, AI systems and communication systems.

Learning Outcomes:

Upon successful completion of the course, the student will be able to:

  1. Understand high-speed wireline channel properties and communications techniques
  2. Understand link system design utilizing statistical bit-error-rate analysis and modeling tools.
  3. Understand the design specifications and implementation details of high-speed SERDES circuits such as drivers, receivers, equalizers, and clocking systems
  4. Understand the design specifications and implementation details of high-speed digital-to-analog and analog-to-digital converters

Schedule:

Day 1 Morning

9-9:50 Introduction

  1. Introduction
  2. Analog Wireline Transceivers
  3. Long Reach (LR) DAC/ADC-DSP Transceivers
  4. High-Performance Data Converters

10-10:50 Wireline Channel Components and Communication Techniques

  1. 200+ Gb/s LR Channel Environment
  2. S-parameter Channel Example
  3. ISI, Pulse Response, and Peak Distortion Analysis
  4. System Noise Modeling

11-12 Equalization System Analysis

  1. TX FFE
  2. RX FFE
  3. CTLE
  4. DFE

Day 1 Afternoon

13-13:50 Wireline Transmitter Circuits

  1. Current and Voltage-Mode Drivers
  2. Swing Enhancement Techniques

14-15:15 Wireline Transmitter Circuits

  1. Analog FFE TX
  2. Impedance Control

15:30-17 Wireline Transmitter Circuits

  1. Pad Bandwidth Extension
  2. High-Speed Serializers
  3. Predriver Bandwidth Extension

17:10-18 High-Speed DAC & Digital FFE

  1. Current-Mode DAC TX
  2. Voltage-Mode DAC TX
  3. Digital TX FFE

Day 2 Morning

9-9:50 Wireline Receiver Circuits

  1. Receiver Front-End Architecture
  2. Input Bandwidth Extension Networks
  3. Low-Frequency Equalization

10-10:50 Wireline Receiver Circuits

  1. Continuous-Time Linear Equalizers
  2. Variable Gain Amplifiers
  3. AFE Linearity

11-12 Wireline Receiver Circuits

  1. Clocked Comparators
  2. Analog Link Sensitivity Analysis
  3. Deserializers

Day 2 Afternoon

13-13:50 RX Analog FFE, DFE, and Equalization Adaptation

  1. RX FFE
  2. Decision Feedback Equalizer
  3. Equalization Adaptation Techniques

14-15:15 High-Speed Time-Interleaved ADCs

  1. ADC/DSP-Based Receiver Motivation
  2. ADC Resolution Requirements & Topologies
  3. Sampling Circuits

15:30-17 ADC Circuits

  1. SAR ADC Circuits
  2. Flash ADC Circuits

17:10-18 Time-Interleaved ADC Calibration Techniques

Day 3 Morning

9-9:50 Digital RX Equalization

  1. Digital FFE
  2. Digital DFE
  3. MLSD

10-10:50 PLL Clock Generation

  1. PLL Overview
  2. Analog Charge Pump PLL

11-12 PLL Clock Generation

  1. Digital PLL
  2. Time Domain Modeling

Day 3 Afternoon

13-13:50 Wireline PLL Examples

14-15:15 Clock Distribution, Multi-Phase Generation/Calibration, and CDR Overview

  1. Clock Distribution
  2. Multi-Phase Generation
  3. Multi-Phase Calibration
  4. CDR Overview

15:30-17 Clock and Data Recovery Systems

  1. Phase Detectors
  2. Analog PLL-based CDR
  3. Digital PLL-based CDR
  4. Dual-Loop CDRs
  5. PIs & DLLs
  6. Jitter Transfer, Generation, and Tolerance

17:10-18 Alternative SERDES Transceivers – Looking Forward

  1. 100+ Gb/s LR Transceiver Trends
  2. Higher-Order PAM
  3. Simultaneous Bidirectional
  4. Discrete Multitone
  5. Multicarrier
  6. Co-Packaged Optics

Bonus Material

PLL Building Blocks

  1. PFD
  2. Charge Pump
  3. Loop Filter
  4. Time-to-Digital Converters
  5. VCOs & DCOs
  6. Dividers

For registration, click here