Charge-Recycling based Design Paradigm for Efficient and Secure RF-Powered IoT Devices

Energy autonomy is a fundamental challenge facing future Internet-of-things (IoT). Relying on existing battery technologies is not only impractical, but also insufficient due to stringent constraints on form factor and limited power densities of conventional charge storage techniques. Wireless/RF power harvesting has recently received considerable attention due to the ubiquity of RF energy around the world such as mobile phones, TV/radio broadcast, and mobile base stations. Applications that rely on dedicated wireless power sources are also increasingly more common. Examples include RFID systems with an active reader, wireless sensor nodes with a dedicated exciter, and implantable devices for healthcare that rely on near-field inductive coupling-based power harvesting. A primary issue in these devices is the scarcity of available power. As such, wirelessly harvested power is typically not sufficient for expensive computational tasks such as encryption and data compression. Furthermore, these devices lack the resources to implement hardware-based root-of-trust. In this talk, I will present a novel vision on developing an efficient and secure computing paradigm for wirelessly powered IoT devices. The proposed method investigates the direct use of harvested AC power by leveraging charge-recycling adiabatic circuit design techniques. The proposed approach increases the energy efficiency by more than an order of magnitude while enhancing critical hardware security characteristics such as resistance to power side-channel attacks and reverse engineering attacks.

 

Emre Salman received the B.S. degree in microelectronics engineering from Sabanci University, Istanbul, Turkey, in 2004, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, NY, USA, in 2006 and 2009, respectively. Since 2010, he has been with the Department of Electrical and Computer Engineering, Stony Brook University (SUNY), NY, USA, where he is currently an Associate Professor. His broad research interests include analysis, modeling, and design methodologies for integrated circuits and VLSI systems with applications to energy-efficient and secure computing, Internet of things with energy harvesting, and implantable devices. He was with Sabanci University as a Visiting Professor during Spring 2020 and with the Air Force Research Labs as a Visiting Faculty Researcher during Summer 2021. He is the leading author of a comprehensive tutorial book titled High Performance Integrated Circuit Design (McGraw-Hill, 2012, Chinese translation, 2015). Dr. Salman was a recipient of the National Science Foundation CAREER Award in 2013, the Outstanding Young Engineer Award from IEEE Long Island, NY, USA, in 2014, and the Technological Innovation Award from IEEE Region 1 in 2018. He was selected as Distinguished Lecturer of the IEEE Circuits and Systems (CAS) Society for 2023 and 2024. He also received multiple outreach initiative awards from the IEEE CAS Society. He currently serves as the Americas Regional Editor for the Journal of Circuits, Systems and Computers, on the Editorial Board of IEEE Transactions on Emerging Topics in Computing, and on the organizational/technical committees of various IEEE and ACM conferences. He previously served as the Chair (2020-2022) for the VLSI Systems and Applications Technical Committee (VSA-TC) of the IEEE CAS Society.

 

Accuracy Improvement of the Analog Integrated Circuits

46954 – Accuracy Improvement of the Analog Integrated Circuits

February 26-28/2023, 9:00 a.m.

Auditorium 1003, Meyer Bld

 

Dr. Vadim Ivanov, Texas Instruments

Instructor: Vadim Ivanov 
Teaching assistant: Itamar Melamed
Lectures: 13 hours, 3 days
Academic points: 1pts
Exam: TBD
Course Fee : 1700$ (See membership options)

For registration click here 

*Registration is open until February 20, 2023

 

Course Content:

In 1951 Bernard Tellegen proved that set of an ideal amplifier, reference, limiter, and RC network
is functionally sufficient for the implementation of any analog functions. It has started a neverending quest to design ideal amplifiers and references. The most accurate voltage references use
the bandgap voltage of the silicon. Out of many options, the de facto standard of an ideal amplifier
is an operational amplifier. Operational amplifiers and bandgap voltage references have been the
first analog ICs in production (since the 1960-s), now with >20,000 types of such ICs available
from almost every semiconductor company and enjoying multi-billion sales just for stand-alone
ICs.
This course will start with an overview of the analog design methodology based on feedback
control of every important parameter in the system. While every feedback loop may be unstable,
we will demonstrate ways to verify and guarantee the stability of the resulting multiloop system.
This methodology will be illustrated with multiple non-trivial examples of current mirrors with
unmeasurable high output impedance; transconductors with wide input range, any load-stable
LDOs with instant load regulation.
Based on this methodology, we will proceed with the in-depth design of the bandgap voltage
references in different processes and for different applications. We will consider embedded
references in digital systems, references for the highest state-of-the-art accuracy, and references
with nanopower consumption. In addition to the circuit design and tradeoffs between
noise/consumption/settling time, we will discuss the challenges with testing, trimming, and
packaging.
The next part of the course is dedicated to improving all OpAmp parameters. These include
speed-to-power ratio, noise, CMRR and PSRR, and input and output voltage range. We will
consider offset and offset temperature drift trimming as well as structures and circuits for offset
elimination by auto-zeroing and chopping.

Topics per Day:

Day 1 (4 academic hours): Structural design methodology and
practical frequency compensation
Discussed are the rules of generating circuit solutions with desired analog functionality out of an
immense variety of options. Design starts with a graphic presentation of the problem with signal
flow graphs or block diagrams, then changing it to the form where everything necessary is
controlled with a dedicated feedback loop, and, finally, implementing the structure using an
elementary cell library. The resulting circuit comprises multiple feedback loops. Interaction
between these loops makes frequency compensation of such a system non-trivial task,
unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which
may cause conditional stability and complicated compensation.
We will consider system structure design for stability, and additional elementary circuit cells to
the textbook set, resulting in achieving unconditional system stability when component
parameters vary, and when load and signal source impedance is not well defined.
Examples include LDOs stable with any load capacitance, transconductors with wide (few volts)
input voltage range, and multistage operational amplifiers.
Day 2 morning (2 academic hours): Bandgap voltage references
Discussed are error sources of the bandgap voltage references and techniques for improving their
accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with
chopping offset elimination, output buffer with mOhm output impedance and fast settling on load
changes; single- dual and triple temperature trimming; packaging requirements; testing and
application particulars. Also presented circuit solutions for reverse bandgap reference,
operational from 0.9V supply, and reference structure and implementations with nanoampere
consumption.
Day 2 afternoon and Day 3 (7 academic hours): Operational amplifier
speed, accuracy, and consumption improvement
Discussed are circuit techniques to improve all essential parameters of the Operational Amplifiers.
Most circuit techniques shown have been previously published only in patents and applications.
Examples include input stage design for low offset, noise, unmeasurable PSRR and CMRR, input
common-mode voltage range; ways of improvement OpAmp speed to power ratio; open loop
gain; power supply range both in high- and low-voltage amplifiers; improving offset by a packagelevel trimming, auto-zero, and chopping; achieving high capacitive drive capability; current limit,
temperature protection, POR.

26FEB23 1 09:00 ~ 09:50 Course Introduction,
2 10:00 ~ 10:50 Structural design methodology
3 11:00 ~ 12:00 Structural design methodology
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Practical frequency compensation
6 14:00 ~ 15:15 Practical frequency compensation
7 15:30 ~ 17:00 Practical frequency compensation
8 17:10 ~ 18:00 Q&A
27FEB23 1 09:00 ~ 09:50 Bandgap voltage references
2 10:00 ~ 10:50 Bandgap voltage references
3 11:00 ~ 12:00 Bandgap voltage references
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Operational amplifier speed, accuracy and consumption improvement
6 14:00 ~ 15:15 Operational amplifier speed, accuracy and consumption improvement
7 15:30 ~ 17:00 Operational amplifier speed, accuracy and consumption improvement
8 17:10 ~ 18:00 Q&A
28FEB23 1 09:00 ~ 09:50 Operational amplifier speed, accuracy and consumption improvement
2 10:00 ~ 10:50 Operational amplifier speed, accuracy and consumption improvement
3 11:00 ~ 12:00 Operational amplifier speed, accuracy and consumption improvement
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Operational amplifier speed, accuracy and consumption improvement
6 14:00 ~ 15:15 Operational amplifier speed, accuracy and consumption improvement
7 15:30 ~ 17:00 Q&A
8 17:10 ~ 18:00

Prerequisites:
044137 Electronic Circuits

Recommended prerequisites:
046187 Analog Circuits Design

Grading:

Written exam – 100%

Instructor’s Bio:

MSEE 1980, Ph.D. 1987, both in the USSR. Designed electronic
systems and ASICs for naval navigation equipment from 1980 to
1991 in St. Petersburg, Russia and mixed signal ASICs for sensors,
GPS/GLONASS receivers and for motor control between 1991 and
1995.
Joined Burr Brown, now Texas Instruments, Tucson, in 1996, where
worked on the operational, instrumentation, power amplifiers,
references and switching and linear voltage regulators, and where
he is currently the Operational Amplifier Technologist. Has 126 patents, with more pending, on
analog circuit techniques and authored > 30 technical papers and three books: “Power Integrated
Amplifiers” (Leningrad, Rumb, 1987), “Analog system design using ASICs” (Leningrad, Rumb,
1988), both in Russian, and “Operational Amplifier Speed and Accuracy Improvement”, Springer,
2004

For registration click here

*Registration is open until February 12, 2023

 

 

Circuits and technologies for implantable biomedical devices

Biological processes such as neuronal signaling and cell growth are among the most complex micro- and nano-scale processes in nature. Historically such processes have been studied at the system level because there were no tools available to study individual components of the process. However, cellular-level interfacing is needed to provide a better understanding of the brain and to develop more advanced prosthetic devices and brain-machine interfaces. With semiconductor technology innovations, much recent work has been focused on unraveling biological complexity, but also on driving new diagnoses, treatments, and therapies that are tailored to the individual. One of the drivers behind those innovations is novel CMOS circuits enabling multi-modal, high-precision data collection and analysis at ultra-low power consumption. In this talk, I will present recent biomedical developments based on silicon technology, and I will discuss the requirements, materials, circuit techniques, and design challenges of their ASIC and SoC platforms.

 

Carolina Mora Lopez received her Ph.D. degree in Electrical Engineering in 2012 from the KU Leuven, Belgium, in collaboration with imec, Belgium. From 2012 to 2018, she worked at imec as a researcher and analog designer focused on interfaces for neural-sensing applications. During this time, she was the lead analog designer and project leader of the Neuropixels development project which resulted in the conception and fabrication of the Neuropixels 1.0 and 2.0 neural probes. She is currently the principal scientist and team leader of the Circuits & Systems for Neural Interfaces team at imec, which develops circuits and technologies for electrophysiology, neuroprosthetics and BMI. Her research interests include analog and mixed-signal circuit design for sensor, bioelectronic and neural interfaces. Carolina is a senior IEEE member and serves on the technical program committee of the ISSC conference, ISSCC SRP, VLSI circuits symposium, and ESSCIRC conference.

 

Important: The participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

 

Integrated Circuits and Systems for Immersive Connectivity and Sensing–ICS2

We are heading to an exciting world where the boundaries between the physical world and the digital/virtual world are blurring, and opportunities and possibilities that are unseeable today will be unleashed. This fascinating future world requires drastic technological breakthroughs and innovations. One key requirement is immersive connectivity and sensing with everything. In this talk, I will present our group research activities in integrated circuits and systems advancing this mission in three key pillars: wireline communication/interconnect, sensing, and wireless communication and radar.

 

Dr. Qun Jane Gu received a Ph.D. from the University of California, Los Angeles in 2007. After a couple of years of industry experience, she started her academic career in 2010 at the University of Florida. Since 2012, she has been with the University of California, Davis, where she is currently a professor. Dr. Jane Gu’s group is passionate in high performance RF, mm-wave and THz integrated circuits and systems and its broad applications. The works from her group have won nine best paper awards from international conferences, including four times from IEEE MTT-S International Microwave Symposium (IMS). She has received 2013 NSF CAREER award, 2015 UC Davis Outstanding Junior Faculty Award, 2017 and 2018 Qualcomm Faculty Award, 2019 UC Davis Chancellor Fellow, and 2022-23 Solid-State Circuits Society Distinguished Lecturer. She is a TPC member of solid state conferences RFIC, CICC and ISSCC.

 

Important: The participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

 

Optimizing Emerging Graph Applications Using Hardware-Software Co-Design

A graph is a ubiquitous data structure that models entities and their interactions through the collections of nodes and edges. It is widely employed in several important application domains ranging from social media, navigation tools, search engines, physics simulations, and biology. Despite its prevalence, the performance of graph workloads on commercial platforms is limited. This is mainly due to the irregular nature of memory accesses and convoluted control flow instructions used in graph applications while accessing large amounts of real-world graph data (i.e., billions of nodes/edges). Therefore, there is a pressing need for optimizing the performance of graph workloads.

In this talk, I will present a systematic optimization study of graph workloads running on both static and dynamic graphs. Specifically, I will present two of my most recent works called NDMiner [ISCA 2022] and Mint [MICRO 2022] in detail. NDMiner optimizes the execution of the Graph Pattern Mining (GPM) application. In this work, I will showcase how to combine the benefits of Near Data Processing (NDP) and domain specialization to improve GPM workload performance. Mint, on the other hand, investigates and optimizes a pattern mining application on temporal graphs (a type of dynamic graph), called temporal motif mining. Mint presents a new programming model, hardware accelerator architecture, and domain-specific optimization to significantly improve the performance of mining temporal motifs. In addition to these works, I will briefly tough upon our optimization and detailed benchmarking effort for traditional graph processing algorithms (e.g., PageRank and SSSP) and random walk-based graph learning pipelines (e.g., node classification and link prediction).

 

Nishil Talati recently completed his PhD from University of Michigan, USA. Prior to joining the PhD program, he completed a master’s degree with thesis from Technion, Israel, and an undergraduate degree from BITS Pilani, India. Nishil’s research interests span computer architecture, compilers, and software engineering. Specifically, he has worked on several optimization efforts to improve the memory performance of modern computing systems. One of his recent works was recognized as the best paper award at HPCA 2021.

 

Important: The participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

 

Prof. Filip Tavernier

Using CMOS for Optical Communication

I will discuss the challenge of using CMOS chips in optical communication applications in this talk. Optical communication has many advantages compared to copper and wireless systems. However, the optical-electrical conversion in the receiver typically requires an external photodiode adding volume and cost to the system. I will explain how it is possible to realize fully integrated optical receivers in CMOS using a pn-photodiode or a Schottky photodiode. While the former is only sensitive to 850 nm light, the latter is sensitive to the more abundant 1310 nm and 1550 nm wavelengths. Due to the intrinsically low response of these integrated photodiodes, low-noise readout circuits are required, which I will also discuss.

 

Filip Tavernier obtained the M.Sc. degree in Electrical Engineering and the Ph.D. degree in Engineering Science from KU Leuven, Leuven, Belgium, in 2005 and 2011, respectively. During 20112014, he was Senior Fellow in the microelectronics group at the European Organization for Nuclear Research (CERN) in Geneva, Switzerland. He was involved in chip designs for the upgrade program of the Large Hadron Collider (LHC) experiments. In 2014, he rejoined KU Leuven at the Department of Electrical Engineering (ESAT-MICAS). As of October 2015, he has been a professor within the same department. His main research interests include circuits for optical communication, data converters, DC-DC converters, and chips for cryogenic environments. Filip is a member of the technical program committees of ESSCIRC, CICC, and SBCCI. He has been SSC-L Guest Editor and is the current SSCS Webinar Chair.

 

Important: The participation is free of charge, but registration is required

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All-Digital Phase-Locked Loops (ADPLL)

047003 – All-Digital Phase-Locked Loops (ADPLL)

October  19,20,23  2022

Auditorium 1003, Mayer Bld.

Professor Robert Bogdan Staszweski, University College Dublin, Ireland  

 

Instructor: Prof. Robert Bogdan Staszweski
Teaching assistant: Itamar Melamed
Lectures: 13 hours, 3 days
Academic points: 1pts
Exam: TBD
Course Fee : 1700$ (see membership options)

For registration click here 

*Registration is open until August 18, 2022

 

Course Content:

The past two decades has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and highperformance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer
function precision, settling speed, frequency modulation capability, and amenability to integration with
digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also
exhibits advantages of better performance, lower power consumption, lower area and cost over the
traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced
by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional
phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for
detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an
analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits
are readily estimated and compensated using “free” but powerful digital logic.

Topics per Day:

Days 1 & 2: (7 academic hours) All-Digital Phase-Locked Loop (ADPLL)
Architecture and Implementation
This lecture presents a system-level view of the ADPLL.
1. Principles of phase-domain frequency synthesis
2. ADPLL closed-loop behavior
3. Direct frequency modulation of ADPLL
4. Alternative TX architectures using ADPLL and PA regulator
5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design

Day 3 Morning (3 academic hours): Digitally-controlled oscillator (DCO)
A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based
on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but
with a significant difference in one of the components: instead of continuously tuned varactor (variable
capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed
in either high or low capacitative state. The composite varactor performs digital-to-capacitance
conversion. This lecture presents a circuit and system level views of DCO.

Day 3 Afternoon (3 academic hours): Time-to-digital converter (TDC)
A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital
variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase
is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay
(about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level
implementation issues.

Prerequisites:

  • 044137 Electronic Circuits
  • 044202 Random Signals

Grading:

Written exam – 100%

Recommended Literature and Study Materials:

Book: R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New
Jersey: John Wiley & Sons, Inc., Sept. 2006. ISBN: 978-0471772552.

Instructor’s Bio:

Robert Bogdan Staszewski received the BSc (summa cum laude), MSc and PhD degrees from the University
of Texas at Dallas in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel Network
Systems in Richardson, TX, USA, working on SONET cross-connect systems for fiber optics
communications. He joined Texas Instruments in Dallas, TX, USA, in 1995 where he was elected
Distinguished Member of Technical Staff (2% of the technical population). Between 1995 and 1999, he
was engaged in advanced CMOS read channel development for hard disk drives. In 1999 he co-started a
Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally intensive
approaches to traditional RF functions for integrated radios in deep-submicron CMOS. He served as a CTO
of the DRP group between 2007 and 2009. In 2009, he joined Delft University of Technology in the
Netherlands where he is currently a guest Full Professor. Since 2014, he has been a Full Professor with
University College Dublin in Ireland. He has authored and co-authored seven books, 11 book chapters,
160 journal and 220 conference publications, and holds 220 issued US patents. His research interests
include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers,
as well as quantum computers. He is an IEEE Fellow and recipient of IEEE Circuits and Systems Industrial Pioneer Award.

For registration click here

*Registration is open until August 18, 2022

 

 

Reliability of Semiconductor Devices

046003 – Reliability of Semiconductor Devices

September  18-20, 2022

Auditorium 280, Mayer Bld.

Dr. Eitan Shauly, Tower Semiconductor  

 

Instructor: Dr. Eitan Shauly
Teaching assistant: Efrat Ordan
Lectures: 13 hours, 3 days
Academic points: 1pts
Exam: TBD
Course Fee : 1700$ (see membership options)

For registration click here 

*Registration is open until August 18, 2022

 

Sylabus:

Detailed overview of reliability failure mechanisms and modeling, from the foundry perspective. Covered Physical and Environmental FEOL and BEOL qualification, Automotive.

Topics:

1 Introduction to Reliability and time degradation

Quality and Reliability; The Reliability bathtub

Failure in time and the acceleration factors (Temp, Voltage, Currents stress)

MTTF (Mean-time-to-Failure), MTBF (Mean-time-between-Failure), FIT (Failure-in-time)

Materials and device degradation vs time – modeling, Competing degradation mechanisms,

Definition of quality and reliability; Yield vs Reliability; Reliability Scaling,

Physical failure mechanisms (Intro): HCI, NBTI, EM, SM, ESD,; Latchup, Soft error

2 EM=Electromigration

Introduction-BEOL reliability concerns; Electromigration–definition; Mass motion and flux modeling; Blech length; Void formation; Stress effects

EM testing and qualification;

Grain Size dependency, Alloys, Barrier metals and other process related performances improvement, N7 and N5 BEOL solutions

EM LT as function of Width and length

EM under AC vs DC conditions; EM scaling limitations

3 SM = Stress Migration in solid Materials

Stress migration, void formation and growth

Stress migration modeling w/ and w/o dielectric all—around

Physics of stress migration; Nucleation; Activation diffusion volume

Resistance change due to voids growth, stress gradients

SIV = Stress-Induced-Voids

SIV modeling;

Layout solution, double via solution; Stacked via sensitivity, effect of misalignment

BEOL dielectric cracking

SM and SIV qualification

4 HCI=Hot Carrier Injection

Carriers’ mobility; currents and voltages in MOSFET under operation: Vt, Id, Ib, Is, CLM, SCE, DIBL,

HCI – mechanism and modeling; DAHC (Drain Avalanche Hot carrier), CHE (Channel hot Electron), SHE (Substrate Hot Electron), others; Lucky Electron Model,

Interface charge generation,

HCI degradation under worse case conditions in planar MOSFETs and FinFETs,

HCI qualification – measurement, analysis and modeling

HCI under AC conditions,

Process solutions to reduce HCI: DDD, spacer with LDD implant, HALO/Pockets;

HCI scaling and integration

5 NBTI=Negative-Bias-Temperature-Instability,

Degradation Mechanism and modeling; Interface traps; The Reactive-Diffusion (R-D) degradation model, PBTI;

Stress time and degradation saturation; NBTI recovery; Dynamic NBTI

Qualification and modeling; NBTI Temperature dependency; NBTI Voltage exponential dependency; Voltage/Field acceleration factor

Process dependency; Boron Penetration, ; Oxynitridization, DPN; Fluorine passivation,

6 GOI=Gate Oxide Integrity,

GOX scaling, interfaces, Leakage; Tunneling, TAT, Qbd, Vbd,; Layout sensitivity;

Weibull distribution

Charge inside GOX, C-V;

Vbd; SBD, HBD,

TDDB – physical mechanisms, IBM modeling,

Process Enhancement GOI

Capacitors reliability, with Oxide-Nitride-Oxide, Nitride, Ta2O5; HKMG (Hf-based); TDDB of FinFETs,

TDDB – Qualification and Modeling

IMD-TDDB

7 PID=Plasma Induced Damage,

The mechanism of PID; Plasma non-uniformity, shading

Degradation of dielectric layers during PID

Antenna Ratio: traditional definition; Antenna rules, calculations and examples; Limitation of the traditional ratio; Cumulative plasma damage

PID dependency on integration flow; PID dependency on Gate oxide;

PID stress and measurement methods, PID structures

Protection: bridging, protective diode; Well charging, protection

8 Environmental qualification and the foundry responsibility

Foundry TQV for platform development; SRAM TEG: structure, scaling, operation, layout

Level-2 qualification – Environmental tests

·       Early Life Failure Rate (ELFR) – calculation

·       Burin-In for screening

·       Random failures, x-ray soft error,

·       High-temperature operating life (HTOL)

·       Biased temperature and humidity (THB, 85/85)

·       Temperature cycling (TMCL)

·       Autoclave

9 Qualification; The fabless/foundry reliability and qualification “relationship”,

The foundry TQV for qualification and WLR in HVM;

Reliability characterization; JEDEC JP001 (1, 2, 3)

Examples for foundry physical reliability qual plan and results

Additional qualification needs (PID, DRV, CA, Cp/Cpk)

10 Reliability for Automotive;

IoT, Automotive, connectivity. Examples for different Automotive applications

Different qualification requirements for Automotive;

Reliability for Automotive; Cumulative failure and life-time

The mission profile; AEC-Q100; ZEVI, Environmental qualification and Burn-In

Quality and Manufacturing for Automotive; Risk management; IATF16949; The Zero-defect program’ Process Control for Automotive’ Continuance Improvement plan’ 8D report, Failure Analysis capabilities

DfA – Design-for-Automotive; Devices, rules, Guidelines and DfM’ SPICE modeling – Aging’ IPs, ISO26262’ ASIL, Safety Function’ Trace and tractability

11 ESD=Electrostatics Discharge,

ESD and Triboelectric; The (cost) impact of ESD; The level of voltage build-up, examples for failures,

ESD Prevention and protection,

ESD Modeling; HBM; MM; CDM

ESD Protection; example

 

References:

  • Reliability and Failure of Electronic Materials and Devices, Milton Ohring, Academic Press (1998)
  • Reliability Wearout Mechanisms in Advanced CMOS Technology (IEEE Press Series on Microelectronic Systems, Alvin W. Strong et al., John Wiley (2009)
  • Up to date list of papers.

Expected Results:

Fulfilling course requirements student is expected to be able to:

  1. Understand the different reliability mechanisms in CMOS devices,
  2. Understand the dependencies between the process and the stress conditions in the field on the failure rate
  3. Fully characterize and analyze the reliability performance and figure of merits of different devices, by carful understanding the different mechanisms and the reliability characterization.
  4. Deep understanding of the way the semiconductor devices operates under stress (transistors, capacitors, resistors and more) thus how to optimize them to achieve the needed performance, with emphasize on reliability for automotive

Prerequisites:

  • 044231 Electron Devices 1 (MOS)

Assignments:

The course will consist of: lectures, self-practice exercises (35% of the grade), and a final exam (65% of the grade).

Course schedule:

18-Sep’22 1 09:00 ~ 09:50 Course Introduction,
Introduction to Reliability and time degradation, (TAF, CAF, VAF), modeling
2 10:00 ~ 10:50 Physical failure mechanisms: HCI, NBTI, EM, SM, GOI, ESD, others
3 11:00 ~ 12:00 Electromigration: definition; Mass motion and flux modeling; Blech length; Void formation; Stress effects
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Electromigration – testing and qualification;
6 14:00 ~ 15:15 Electromigration: Grain Size dependency, Alloys, Barrier metals and other process related performances improvement, N7 and N5 BEOL solutions
7 15:30 ~ 17:00 Electromigration: LT as function of Width and length, AC vs DC conditions; EM scaling limitations.
Stress Migration: Introduction
8 17:10 ~ 18:00 Stress Migration: void formation and growth; SIV modeling; Layout solution, double via solution; Stacked via sensitivity, effect of misalignment
19-Sep’22 1 09:00 ~ 09:50 Hot-Carrier-Injection: mechanism and modeling; DAHC (Drain Avalanche Hot carrier), CHE (Channel hot Electron), SHE (Substrate Hot Electron), others; Lucky Electron Model,
2 10:00 ~ 10:50 HCI: HCI degradation under worse case conditions in planar MOSFETs and FinFETs, qualification – measurement, analysis and modeling, Process solutions to reduce HCI: DDD, spacer with LDD implant, HALO/Pockets; Aging
3 11:00 ~ 12:00 Negative-Bias-Temperature-Instability: Degradation Mechanism and modeling; Interface traps; The Reactive-Diffusion (R-D) degradation model, PBTI;
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 NBTI: Stress time and degradation saturation; NBTI recovery; Dynamic NBTI; Qualification and modeling; Process dependency; Boron Penetration, ; Oxynitridization, DPN; Fluorine passivation,
6 14:00 ~ 15:15 Gate Oxide Integrity: GOX scaling, interfaces, Leakage; Tunneling, TAT, Qbd, Vbd,; Layout sensitivity;
7 15:30 ~ 17:00 GOI: Weibull distribution; Charge inside GOX, C-V; TDDB – physical mechanisms, IBM modeling,
8 17:10 ~ 18:00 GOI / Tirgol
20-Sep’22 1 09:00 ~ 09:50 GOI: Process Enhancement GOI; Oxide-Nitride-Oxide, Nitride, Ta2O5; HKMG (Hf-based);
2 10:00 ~ 10:50 GOI:  TDDB of FinFETs, TDDB – Qualification and Modeling, IMD-TDDB
3 11:00 ~ 12:00 Plasma Induced Damage: The mechanism of PID; Plasma non-uniformity, shading, Antenna Ratio: traditional definition; Antenna rules, calculations and examples; Limitation of the traditional ratio; Cumulative plasma damage; Protection: bridging, protective diode; Well charging, protection
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Technology qualification: TEG, TQV, ELFR, Burn-In, HTOL, THB, 85/85
6 14:00 ~ 15:15 Technology qualification: TMCL, JEDEC JP001
7 15:30 ~ 17:00 Automotive: Reliability, AEC-Q100, ZEVI, Mission Profile, Quality, IARF16949, DFA, IPs, ISO 26262
8 17:10 ~ 18:00 Electrostatics Discharge: Mechanism, examples for failures, Prevention and protection, HBM, MM, CDM

 

Lecturer Bio:

Dr. Eitan N. Shauly received the B.Sc. degree in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, in 1989, and M.Sc. and Ph.D. degrees in materials engineering from the Technicon — Institute of Technology, Haifa, in 1995 and 2001, respectively. He has worked for Tower Semiconductor since 1989. During 1989–1994 he was a diffusion and ion implantation engineer. During 1994–1997 he was a device/Integration engineer, focusing on process integration and process modeling. Since 1998 he is doing integration, focusing on platform development, design rules, Design-for-Manufacturing and Automotive. Dr. Shauly is also teaching at the faculty of Material Engineering, Technicon Haifa, courses related to VLSI technology: “VLSI processing” and “CMOS Devices and Integration”.

 

For registration click here 

*Registration is open until August 18, 2022

Michal Kagan

ACRC workshop ENTREPRENEURSHIP IN SEMICONDUCTORS with MICHAEL KAGAN

 

Michael Kagan is NVIDIA CTO (Chief Technology Officer) since May 2020. He joined NVIDIA through Mellanox acquisition.

Michael Kagan was previously Mellanox CTO and a co-founder of Mellanox that was founded in April 1999.

From 1983 to April 1999, Mr. Kagan held a number of architecture and design positions at Intel Corporation. While at Intel Corporation, Mr. Kagan was architect of the i860XP vector processor, managed Pentium MMX design, and managed the architecture team of the Basic PC product group.

Mr. Kagan holds a BSc. in Electrical Engineering from the Technion — Israel Institute of Technology.

Important: registration is required

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