Danielle Griffith, Texas Instruments, Dallas, Texas

Towards zero: Power consumption trends in low data rate wireless connectivity products

The low power IoT market began in earnest in 1999 with the launch of the first commercial Bluetooth® device.  Analysis of >200 datasheets and published IEEE conference and journal papers shows that since then, active power consumption for these low data rate radios has reduced by 20x, while sensitivity has improved by 15dB.  Large power reductions have also been seen in metrics such as the standby and BLE-1s connection interval currents.  This talk will explore which innovations have made this possible, and what power consumption trends we can we expect in the future.   Questions to be addressed include:  How does power consumption trade off with data rate, transmit power and receiver sensitivity? How low power is low enough? Where do wakeup radios and energy harvesting fit into this?  Where will it all end?

 

Danielle Griffith received the B.S.E.E. and M.Eng. degrees from the Massachusetts Institute of Technology, Cambridge.   In 2003, she joined Texas Instruments in Dallas, Texas and is a Fellow in the Connectivity business unit.  Her current focus areas are circuits and architectures for efficient wireless systems, low power oscillators and MEMS circuitry.   She has published a book chapter and >50 papers, most of them in IEEE journals or conferences.   Danielle holds 19 issued US patents and has given numerous university and IEEE conference tutorial and workshop sessions.  She has been a member of the Technical Program Committees for the IEEE RFIC Symposium (2014-2015), IEEE International Solid-State Circuits Conference (2016-2019), and the IEEE VLSI Symposium (2019-2020).  She is a senior member of the IEEE, an associate editor of the IEEE Journal of Solid-State Circuits since 2020, and has been selected as Distinguished Lecturer of the IEEE Solid-State Circuits Society for 2021–2022.

 

Important: The participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

Microelectronic Systems for Improved Quality of Life

Microelectronic Systems for Improved Quality of Life

Microelectronic revolutions come in waves that are driven by necessity. Currently, the aging population is creating a need for various kinds of electronic systems to improve their quality of life. These include the restoration of lost functionality via electronic implants, better health screening technology and non-invasive monitoring in the home environment. This talk presents work that has been done towards addressing these needs, whether it be through the development of new required building blocks or through the development of more complex systems that combine custom built hardware and software. In particular the talk covers work done towards developing a vestibular implant for balance restoration, a single chip low-power imager for a bionic eye, a cancer screening capsule for detecting early-stage carcinomas in the small intestine, a bio-inspired acoustic scene analysis system, the development of the ElectroUteroGraph, as well as the use of custom chips for the design of adaptive metamaterials.

Julius Georgiou (IEEE M’98-SM’08) is an Associate Professor at the University of Cyprus. He received his M.Eng degree in Electrical and Electronic Engineering and Ph.D. degree from Imperial College London in 1998 and 2003 respectively. For two years he worked as Head of Micropower Design in a technology start-up company, Toumaz Technology.  In 2004 he joined the Johns Hopkins University as a Postdoctoral Fellow, before becoming a faculty member at the University of Cyprus from 2005 to date. He is one of the co-founders of AJM Med-i-CAPs Ltd.

Prof. Georgiou is a member of the IEEE Circuits and Systems Society, is the Chair of the IEEE Biomedical and Life Science Circuits and Systems (BioCAS) Technical Committee, as well as a member of the IEEE Circuits and Systems Society Analog Signal Processing Technical Committee. He served as the General Chair of the 2010 IEEE Biomedical Circuits and Systems Conference and is the Action Chair of the EU COST Action ICT-1401 on “Memristors-Devices, Models, Circuits, Systems and Applications – MemoCIS”. Prof. Georgiou was an IEEE Circuits and Systems Society Distinguished Lecturer for 2016-2017. He also was an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems, an Associate Editor of the Frontiers in Neuromorphic Engineering Journal and a Guest Editor for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems, for Programmable Metamaterials and also Circuits and Systems for Smart Agriculture. He is a recipient of a best paper award at the IEEE ISCAS 2011 International Symposium and at the IEEE BioDevices 2008 Conference. In 2016 he received ONE Award from the President of the Republic of Cyprus for his research accomplishments.

Microelectronic Systems for Improved Quality of Life

Microelectronic Systems for Improved Quality of Life

Microelectronic revolutions come in waves that are driven by necessity. Currently, the aging population is creating a need for various kinds of electronic systems to improve their quality of life. These include the restoration of lost functionality via electronic implants, better health screening technology and non-invasive monitoring in the home environment. This talk presents work that has been done towards addressing these needs, whether it be through the development of new required building blocks or through the development of more complex systems that combine custom built hardware and software. In particular the talk covers work done towards developing a vestibular implant for balance restoration, a single chip low-power imager for a bionic eye, a cancer screening capsule for detecting early-stage carcinomas in the small intestine, a bio-inspired acoustic scene analysis system, the development of the ElectroUteroGraph, as well as the use of custom chips for the design of adaptive metamaterials.

 

Julius Georgiou (IEEE M’98-SM’08) is an Associate Professor at the University of Cyprus. He received his M.Eng degree in Electrical and Electronic Engineering and Ph.D. degree from Imperial College London in 1998 and 2003 respectively. For two years he worked as Head of Micropower Design in a technology start-up company, Toumaz Technology.  In 2004 he joined the Johns Hopkins University as a Postdoctoral Fellow, before becoming a faculty member at the University of Cyprus from 2005 to date. He is one of the co-founders of AJM Med-i-CAPs Ltd.

Prof. Georgiou is a member of the IEEE Circuits and Systems Society, is the Chair of the IEEE Biomedical and Life Science Circuits and Systems (BioCAS) Technical Committee, as well as a member of the IEEE Circuits and Systems Society Analog Signal Processing Technical Committee. He served as the General Chair of the 2010 IEEE Biomedical Circuits and Systems Conference and is the Action Chair of the EU COST Action ICT-1401 on “Memristors-Devices, Models, Circuits, Systems and Applications – MemoCIS”. Prof. Georgiou was an IEEE Circuits and Systems Society Distinguished Lecturer for 2016-2017. He also was an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems, an Associate Editor of the Frontiers in Neuromorphic Engineering Journal and a Guest Editor for the IEEE Journal on Emerging and Selected Topics in Circuits and Systems, for Programmable Metamaterials and also Circuits and Systems for Smart Agriculture. He is a recipient of a best paper award at the IEEE ISCAS 2011 International Symposium and at the IEEE BioDevices 2008 Conference. In 2016 he received ONE Award from the President of the Republic of Cyprus for his research accomplishments.

When: Monday, April 11, 2022 at 10:00 (Israel Time)

Where: Meyer 861

We hope to see you there in person, otherwise you can join us via this link:

Launch Meeting – Zoom

 

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

Edge of Chaos behind Smale’s Silence-to-Regular Beating Transition Paradox

In this seminar a bio-inspired memristor cellular nonlinear network, reproducing qualitatively the same counterintuitive phenomenon observed by Smale, is first designed. As compared to the 8th-order biological system in [1], the proposed array of two identical diffusively-coupled cells [4] features just 4 degrees of freedom, hosting 2 volatile locally-active niobium oxide-based threshold switches [5]-[6] from NamLab [7], and 2 capacitors, besides 3 resistors, and 2 batteries, to form the simplest everreported open physical system undergoing diffusion-driven instabilities with dynamic pattern formation. Then, a rigorous circuit- and system-theoretic study, based upon linearization analysis and large-signal phase-portrait investigations, sheds light on the local and global dynamics of the uncoupled cell, to demonstrate that, when the latter is biased on a globally asymptotically-stable and locally-active operating point, does the paradoxical phenomenon, reported by Smale in [1], emerge in the proposed bio-inspired array, under a sufficiently-strong resistive coupling condition. All in all, this presentation sheds light on the pivotal role that nonlinear circuit and system theory is expected to assume, in the years to come, to support circuit design with intrinsically-nonlinear nanodevices, and on the relevance of the adoption of solid-state memristive small-signal amplifiers ], [5 operating according to similar principles as the sodium and potassium ion channels in neuronal axon membranes [8], to reproduce the complex dynamics of biological networks in electronic systems.

 

Alon Ascoli (IEEE Senior Member) received a Habilitation as Full Professor in Fundamentals of Electrical Engineering from Technische Universität Dresden (TU Dresden) in 2022, a Ph.D. Degree in Electronic Engineering from University College Dublin in 2006, and a First-Class Honours Master’s Degree in Electronic Engineering from Universita’ degli Studi Roma Tre in 2001. He currently holds a tenure faculty position at the Institute of Principles of Electrical and Electronic Engineering of TU Dresden. He develops system-theoretic methods for the analysis and design of bio-inspired memristive/memcapacitive circuits bound to enable progress in electronics beyond the Moore era, and to allow the plausible reproduction of complex phenomena emerging in biological systems. He was honoured with Best Paper Awards from IJCTA in 2007 and MOCAST in 2020. In April 2017 he was conferred the habilitation title as Associate Professor in Electrical Circuit Theory from the Italian Ministry of Education. He is a member of the Scientific Advisory Board of the Chua Memristor Center, and of the IEEE Nanoelectronics and Gigascale Systems Technical Committee (Nano-Giga TC). He was the Chair of the IEEE Cellular Nonlinear Networks and Array Computing (CNNAC) TC from 2019 to 2021. Since 2021 he is the Chair of the new-born IEEE Cellular Nonlinear Networks and Memristive Array Computing (CNN-MAC) TC.

 

Important: The participation is free of charge, but registration is required

Registration for “Edge of Chaos behind Smale’s Silence-to-Regular Beating Transition Paradox”

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

 

Reality Labs: Augmented Reality silicon challenges at and research directions

Reality Labs: Augmented Reality silicon challenges at and research directions

Augmented reality (AR) is a set of technologies that will fundamentally change the way we interact with our environment. It represents a merging of the physical and the digital worlds into a rich, context aware and accessible user interface delivered through a socially acceptable form factor such as eyeglasses. One of the biggest challenges in realizing a comprehensive AR experience are the performance and form factor requiring new custom silicon. Innovations are mandatory to manage power consumption constraints and ensure both adequate battery life and a physically comfortable thermal envelope. This presentation reviews Augmented Reality applications at Facebook Reality Labs and Silicon challenges.

 

Edith Beigné is the Research Director of AR/VR Silicon at Meta Reality Labs where she leads research projects driving the future of AR devices. Her main research interests are low power digital and mixed-signal circuits and design with emerging technologies. Over the past 20 years, she has been focusing her research on low power and adaptive circuit techniques, exploiting new design techniques and advanced technology nodes for different applications ranging from high performance multi-processors to ultra-low power SoC, and, more recently, AR/VR applications. She is the chair of ISSCC 2022 and part of ISSCC TPC since 2014, she was part of VLSI symposium TPC between 2015 and 2020. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor since 2018. She visited Stanford University in 2018 to research on emerging technologies and new architectures.

Important: The participation is free of charge, but registration is required

Registration for “Reality Labs: Augmented Reality silicon challenges at and research directions”

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

Electronic Design Automation for Emerging Technologies

Electronic Design Automation for Emerging Technologies

The continued scaling of horizontal and vertical physical features of silicon-based complementary metal-oxide-semiconductor (CMOS) transistors, termed as “More Moore”, has a limited runway and would eventually be replaced with “Beyond CMOS” technologies. There has been a tremendous effort to follow Moore’s law but it is currently approaching atomistic and quantum mechanical physics boundaries. This has led to active research in other non-CMOS technologies such as memristive devices, carbon nanotube field-effect transistors, quantum computing, etc. Several of these technologies have been realized on practical devices with promising gains in yield, integration density, runtime performance, and energy efficiency. Their eventual adoption is largely reliant on the continued research of Electronic Design Automation (EDA) tools catering to these specific technologies. Indeed, some of these technologies present new challenges to the EDA research community, which are being addressed through a series of innovative tools and techniques. In this tutorial, we will particularly cover the two phases of EDA flow, logic synthesis, and technology mapping, for two types of emerging technologies, namely, in-memory computing and quantum computing.

Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India, MSc. from ALaRI, Switzerland, and Ph.D. from RWTH Aachen in 2000, 2002, and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September 2014, Anupam was appointed as an Assistant Professor in SCSE, NTU, where he got promoted to Associate Professor with Tenure from August 2019. His research interests are in Application-specific architecture, Electronic Design Automation, and Security. Anupam is an Associate Editor of IEEE Embedded Systems Letters and series editor of Springer Book Series on Computer Architecture and Design Methodologies. Anupam received Borcher’s plaque from RWTH Aachen, Germany for outstanding doctoral dissertation in 2008, nomination for the best IP award in the ACM/IEEE DATE Conference 2016 and nomination for the best paper award in the International Conference on VLSI Design 2018 and 2020. He is a fellow of Intercontinental Academia and a senior member of IEEE and ACM.

Important: The participation is free of charge, but registration is required

Registration on “Electronic Design Automation for Emerging Technologies”

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website

“Bringing ML to the extreme edge: a story of co-optimizing processor architectures, scheduling and models” by Prof. Marian Verhelst

Deep neural network inference comes with significant computational complexity, making their execution until recently only feasible on power-hungry server or GPU platforms. The recent trend towards real-time embedded neural network processing on edge and extreme edge devices requires a thorough cross-layer optimization. The talk will analyze what impacts NN execution energy and latency. Subsequently, we will present different research lines of Prof. Verhelst’s lab exploiting and jointly optimizing NPU/TPU processor architectures, dataflow schedulers and conditional, quantized neural network models for minimum latency and maximum energy efficiency. This includes precision-scalable fully-digital designs, as well as compute-in-memory processors. Finally, this talk will make a case for more methodological design space exploration in the vast optimization space of embedded NN processors, using the ZigZag framework.

Marian Verhelst is a full professor at the MICAS laboratories of the EE Department of KU Leuven. Her research focuses on embedded machine learning, hardware accelerators, HW-algorithm co-design and low-power edge processing. Before that, she received a PhD from KU Leuven in 2008, was a visiting scholar at the BWRC of UC Berkeley in the summer of 2005, and worked as a research scientist at Intel Labs, Hillsboro OR from 2008 till 2011. Marian is a topic chair of the DATE and ISSCC executive committees, TPC member of VLSI and ESSCIRC  and was the chair of tinyML2021 and TPC co-chair of AICAS2020. Marian is an IEEE SSCS Distinguished Lecturer, was a member of the Young Academy of Belgium, an associate editor for TVLSI, TCAS-II and JSSC and a member of the STEM advisory committee to the Flemish Government. Marian currently holds a prestigious ERC Starting Grant from the European Union, was the laureate of the Royal Academy of Belgium in 2016, and received the André Mischke YAE Prize for Science and Policy in 2021.

Important: The participation is free of charge, but registration is required

/registration-marian-verhelst/

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website

“Mixed-Signal Computing for Deep Neural Network Inference” – webinar by Prof. Boris Murmann from Stanford University, USA

Modern deep neural networks (DNNs) require billions of multiply-accumulate operations per inference. Given that these computations require relatively low precision, it is feasible to consider analog arithmetic, which can be more efficient than digital in the low-SNR regime. However, the scale of DNNs favors circuits that leverage dense digital memory, leading to mixed-signal processing schemes for scalable solutions. This presentation will investigate the potential of mixed-signal approaches in the context of modern DNN processor architectures, which are typically limited by data movement and memory access. We will show that dense mixed-signal fabrics offer new degrees of freedom that can help alleviate these bottlenecks. In addition, we will derive asymptotic efficiency limits and highlight the challenges associated with data conversion interfaces (D/A and A/D) as well as programmability. Finally, these findings are extended to in-memory computing approaches (SRAM and RRAM-based) that are bound by similar constraints.

Boris Murmann is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has worked as a consultant with numerous Silicon Valley companies. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters and custom circuits for embedded machine learning. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits, an AdCom member and Distinguished Lecturer of the IEEE Solid-State Circuits Society, as well as the Data Converter Subcommittee Chair and the Technical Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He is the founding faculty co-director of the Stanford SystemX Alliance and the faculty director of Stanford’s System Prototyping Facility (SPF). He is a Fellow of the IEEE.

Please sign up and join us on Monday, August 17, 2020 at 17:00 (Israel Day Time). A link to the Zoom session will be provided after registration.

Important: The participation is free of charge, but registration is required /registration-boris-murmann/

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website.