Speaker: Prof. Gabriel Rincon-Mora, Georgia Institute of Technology

Date: September 7, 2026, Monday

Time: 16:00 – 17:30 Israel Time

Location: Zoom

Language: English

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Abstract:

Switched-inductor power supplies are pervasive in electronics. This is because they deliver a large fraction of the power they draw from the input source with an output that is largely independent of the load. Keeping the output steady this way is ultimately the responsibility of the feedback controller. This talk uses insight and intuition to show how hysteretic, timed, and clocked peak/valley loops control their outputs and respond to sudden changes. The presentation also describes when sub-harmonic oscillations surface and how slope compensation suppresses them. It then shows how summing comparators work and how they can contract, offset, and compensate these control loops and how comparators limit their input-to-output translations in continuous conduction and output current in discontinuous conduction. With this background and understanding in hand, designing compact feedback controllers for switched-inductor IoT power supplies is not only possible but also more straightforward.

Bio:

Gabriel Alfonso Rincón-Mora is Motorola Solutions Foundation Professor, Fellow of the National Academy of Inventors (NAI), Fellow of the American Association for the Advancement of Science (AAAS), Fellow of the Institution of Engineering and Technology (IET), and Fellow of the Institute of Electrical and Electronics Engineering (IEEE). He’s received the IEEE Charles A. Desoer Technical Achievement Award, Distinguished Faculty Achievement Award, Charles E. Perry Visionary Award, Three-Year Patent Award, National Hispanic in Technology Award, IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award, IEEE Outstanding Educator Award, Orgullo Hispano Award, Hispanic Heritage Award, State of California Commendation Certificate, and IEEE Service Award. His body of work includes 12 books, 8 handbooks, 4 book chapters, 44 patents, over 200 articles, over 26 commercial power-chip products released to production, 25 educational videos, and over 180 keynote addresses, distinguished lectures, and research seminars. URL: rincon-mora.gatech.edu.

The webinar is free but the registration is required. The Zoom link will be sent after registration.

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Speaker: Prof. Anirban Sengupta, Indian Institute of Technology Indore (IIT Indore)

Date: June 29, 2026, Monday

Time: 16:00 – 17:30 Israel Time

Location: Zoom

Language: English

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Abstract: 

Hardware Trojans in high level synthesis (HLS) generated intellectual property (IP) designs pose significant security threats. The HLS frameworks, while enabling efficient hardware design from high-level descriptions to its respective register transfer level (RTL) counterpart, may introduce security vulnerabilities. These vulnerabilities allow malicious Trojan to be stealthily injected during phases like scheduling, allocation, and mux-interconnect design stage. Compromised HLS frameworks exacerbate this risk, potentially embedding backdoors or degrading IP operation in multiple ways. This presentation will discuss advanced HLS Trojan detection techniques based decision tree classifier-based machine learning model. The presentation will also focus on key hardware IP RTL features that need to be extracted and analyzed, for achieving high detection accuracy with zero false positives for specific trojans considered here, ensuring robust IP security.

Bio: 

Prof. Anirban Sengupta (SMIEEE, FIET, FBCS, FIETE, Ph.D.) is a full Professor in the Department of Computer Science and Engineering at Indian Institute of Technology (IIT) Indore. He has more than 340 publications and patents, including 7 books, to his credit. His is recipient of awards/honors/recognitions such as Distinguished Contributor of IEEE Computer Society, Distinguished Lecturer of IEEE Circuits and Systems Society, Distinguished Lecturer of IEEE Consumer Technology Society, Distinguished Visitor of IEEE Computer Society, ACM India Eminent Speaker, Fellow of IET, Fellow of British Computer Society, Fellow of IETE, IEEE Chester Sall Memorial Consumer Electronics Award, IEEE CESoc Outstanding Editor Award, IEEE CESoc Best Research Award from CEM, Best Research paper Award in IEEE ICCE 2019, IEEE Computer Society TCVLSI Outstanding Editor Award and IEEE TCVLSI Best Paper Award in IEEE iNIS 2017. He held/holds around 20 Editorial positions in IEEE/IET Journal boards. He is consistently ranked in Stanford University’s Top 2 % Scientists globally. Details available at: http://www.anirbansengupta.com/index.php

The webinar is free but registration is required. The Zoom link will be sent after registration.

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Speaker: Prof. Avi Zadok, Technion – Israel Institute of Technology

Date: May 10, 2026

Time: 16:00 – 17:30 Israel Time

Location: Zoom

Language: English

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Abstract: 

Silicon photonics is an essential, enabling technology for modern-day data centers and super computes. In this lecture, I will introduce the basic building blocks of silicon photonic circuits and discuss the current state-of-the-art, challenges and limitations, and comparative merits and drawbacks of this exciting technology. The lecture is intended primarily for non-specialists, interested in a technical introduction to the topic.

Bio:

 Prof. Avi Zadok obtained his Ph.D. in Electrical Engineering from Tel-Aviv University in 2007. He has been with the Faculty of Engineering, Bar-Ilan University between 2009-2024, and joined the Faculty of Electrical and Computer Engineering of the Technion in 2024. His research group is working on photonic integrated circuits with emphasis on silicon, fiber-optics, nonlinear optics, and opto-mechanics. Dr. Zadok published over 200 papers in scientific journals and proceedings of international conferences.

The webinar is free, but registration is required. The Zoom link will be sent after registration.

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Date: April 13, 2026

Time: 18:00 – 19:30 Israel Time

Speaker: Prof. Jason Eshraghian, University of California, Santa Cruz

Language: English

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Abstract

The brain is the perfect place to look for inspiration to develop more efficient neural networks. Inspired by the recurrent dynamics of biological neurons, this talk will present several frontier reasoning LLMs developed in my lab, from software to device deployments. Trained end-to-end in an academic lab on a full production pipeline (data curation, pre-training, to post-training and alignment) these models surpass all leading LLMs from Meta, Google and every other over-resourced company in the ~10-billion parameter regime, despite being ~5x smaller. We have deployed several of our models on neuromorphic hardware at 2-watts, bringing SoTA-level reasoning from the datacenter to the edge.

Bio

Jason Eshraghian is an Assistant Professor and Fulbright Scholar in the Department of Electrical and Computer Engineering at the University of California, Santa Cruz. He is the developer of snnTorch, a Python library with over 500,000 downloads for training spiking neural networks. He is a dual-appointed IEEE CAS and EMBS Distinguished Lecturer, an Associate Editor of APL Machine Learning, the Chair of the IEEE Neural Systems and Applications Technical Committee, has been the recipient of seven IEEE Best Paper Awards, a Scientific Advisory Board Member of BrainChip, and leads the Neuromorphic Agents Team at Conscium.

The webinar is free, but registration is required. The Zoom link will be sent after registration. 

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Date: March 18, 2026 – Wednesday

Time: 17:00 – 18:30 Israel Time

Lecturer: Prof. Bibhu Datta Sahoo, University at Buffalo

Language: English

Abstract: 

The rapid advancements in computing, communication, and networking technologies facilitated by the feature size scaling of transistors, have not only made connected devices, i.e., Internet-of-Things (IoT), possible but also resulted in volumes of data being generated by these devices, which has led to rapid advancements in the area of big-data analytics thereby ushering in a new era of artificial intelligence and machine learning hardware to make smart connected devices. We have reached an inflection point in the design of such smart connected devices: the machine learning hardware designer must look beyond conventional digital computing blocks and possibly revive analog computing. This has led to a new generation of analog designers who are combining conventional analog circuits with approximate computing techniques using conventional CMOS as well as emerging-devices compatible with CMOS to build energy-efficient systems. This talk begins with an overview of various Neural Network Architectures and the computing blocks needed to realize them. FPGA-based Convolutional Neural Network (CNN) architectures for energy-efficient inference engines for image/depth-image classification, and seizure prediction which also reduces the sensor-interface front-end power and the energy-per-bit needed to transmit the sensor information to the inference engine will be discussed next. Hardware techniques for memory augmented neural network (MANN) using novel magneto-electric FETs  (MeFET) will be discussed as well. Various analog dot-product computation methodologies, viz., conductance-based, charge-based, and gm-based will be discussed next. An oscillator-based mixed-signal Spiking Neural Network (SNN) architecture and techniques to facilitate energy-efficient training-on-the-edge will be presented.

Biography: 

Bibhu Datta Sahoo joined the faculty of the UB Department of Electrical Engineering as Professor in Fall 2023. He received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology (IIT), Kharagpur, India, in 1998, the M.S.E.E. degree from the University of Minnesota, Minneapolis, MN, USA, in 2000, and the Ph.D. E.E. Degree from the University of California, Los Angeles in 2009. From 2000 to 2006, he was with DSP Microelectronics Group, Broadcom Corporation, Irvine, CA, where he designed analog and digital integrated circuits for signal-processing applications. From December 2008 to February 2010, he was with Maxlinear Inc., Carlsbad, CA, where he was involved in designing RF Integrated Circuits for CMOS TV tuners. He has been a faculty at IIT Kharagpur, India for 6 years and Amrita University, India for 5 years.  His research interests include mixed signal circuit design, analog computing, and machine learning hardware. He received the 2008 Analog Devices Outstanding Student Designer Award and was the co-recipient of the 2013 CICC Best Paper Award. He was the Associate Editor of IEEE Transactions on Circuits and Systems-II from Aug. 2014 to Dec. 2015. Since Aug. 2019 he has been the Associate Editor of IEEE Open Journal of Circuits and Systems. He is one of the IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2025-2026.

The webinar is free but registration is required.

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Speaker: Tuvia Liran

Date: February 16, 2026 – Monday

Time: 16:00 – 17:30 Israel Time

Language: Hebrew

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Abstract:

Chips are exposed to energetic particles, but in some applications, such as space, the doze of particles is high and hazardous. Protons, ion, neutrons, alpha/beta/gamma particles and X-ray might degrade the performance, shorten lifetime, and might cause hard or soft failures.

The lecture will describe the failure mechanisms and key mitigation techniques. The common mechanisms are TID, SEL, SEU, but there are additional mechanisms that might affect special applications. It is typically not practical to eliminate the failures, but it is practical and achievable to mitigate them significantly.

Mitigation the radiation effects can be done by process, architecture/logic/circuit/layout design, by software/firmware, and by system level mechanical/hardware/software techniques. The key techniques will be presented. The most common mitigation technique, which is implemented during the chip design flow, is named Radiation Hardening By Design (RHBD). This is the main scope of the lecture.

Advanced semiconductor technologies are inherently more immune to radiation effects. However, some circuits, especially those operate at relatively high voltage, might be under-protected, unless mitigated by simple design techniques. Some tips will be provided.

Bio:

Tuvia Liran had >40 years of experience in VLSI development, including analog & digital design, process, testing, Q&R, packaging and more. He wrote 15 patents, mostly on VLSI circuits.
He graduated Bsc in physics, and EE and Msc in electronics from the Technion in the eighties, and since then he was in VLSI industry, and mentoring projects in VLSI lab.
He was co-founder of Ramon.Space, where he was responsible, as CTO, for the development of the technologies for space applications. The components demonstrated extremely high immunity to all radiation effects, and company’s products had been selected for many space missions, including missions to Mars, Asteroids, Jupiter, Saturn, Sun, and many satellites.

He served as navigator in IAF during his military service.

The webinar is free but registration is required. The Zoom link will be sent after registration.

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Date: February 11, 2026 – Wednesday

Time: 17:00 – 18:30 Israel Time

Speaker: Eugene Izhikevich, Founder and CEO of SpikeCore

Language: English

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Abstract: 

Current AI models are a thousand times less energy-efficient than the brain. These models use artificial neural networks (ANNs) requiring GPUs for multiplication of huge matrices. In contrast, spiking neural networks (SNNs) within the human brain do not employ matrix multiplication and dissipate orders of magnitude less energy.

In this talk, Prof. Eugene Izhikevich presents the Spiking Manifesto: a framework for thinking about popular AI models in terms of spiking networks and polychronization, and for interpreting spiking activity within the brain as nature’s way of providing look-up tables. This approach offers a novel approach to develop ANNs in hardware and to build AI models based on innovative architectures. The spiking manifesto provides a path to thousandfold improvements in energy efficiency.

Biography: 

Founder and CEO of SpikeCore, San Diego, California
Founder and Chairman of the Board of Brain Corp, San Diego, California
Founder and Editor-in-Chief of Scholarpedia – the peer-reviewed encyclopedia
Publications: https://scholar.google.com/citations?user=1JeBX-IAAAAJ

The webinar is free, but registration is required. The Zoom session link will be sent after registration. 

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