Abstract: 

Piezoelectric vibration-to-electricity conversion provides a feasible solution to self-sustainability due to its relatively high power density, wider voltage range, and the compatibility with IC technology. In the past decade, we have seen a booming of various interface circuits developed for piezoelectric energy harvesting. The drastic difference between the operating speed of integrated circuits and mechanical vibrations provides a perfect venue for performing nonlinear switching and control in the interface operation with low power, allowing orders of magnitude of improvement in power extracting ability.

This tutorial will cover a wide range of state-of-the-art interface designs and MPPT methods for piezoelectric energy harvesting, while emphasizing the circuit implementation considerations. Specifically, after describing the basic full-bridge and half-bridge rectifiers, the Synchronized-Switch-Harvesting (SSH) technique that is the foundation of all modern nonlinear interface circuits will be introduced. Two major categories, namely, the open-circuit and the short-circuit structures, are then discussed in details. After that, the common MPPT algorithms and implementations will be reviewed. This talk will also cover topics such as non-resonant operations and multiple-input piezoelectric energy harvesting systems.

Bio: 

Ping-Hsuan Hsieh received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, Los Angeles, CA, in 2004 and 2009, respectively. From 2009 to 2011, she was with the IBM T.J. Watson Research Center, Yorktown Heights, NY. In 2011 she joined the Electrical Engineering Department of National Tsing Hua University, Hsinchu, Taiwan, where she is currently an Associate Professor. Her research interests focus on mixed-signal integrated circuit designs for high-speed electrical data communications, clocking and synchronization systems, and energy-harvesting systems.

Prof. Hsieh served in the Technical Program Committee of the IEEE International Solid-State Circuits Conference, and is currently a member of the Technical Program Committees of the IEEE Asian Solid-State Circuits Conference and the IEEE Custom Integrated Circuits Conference. She served as an Associate Editor for the IEEE Internet of Things Journal from 2014 to 2018, a Guest Editor for the IEEE Journal of Solid-State Circuits Special Issue in 2021, and is currently an Associate Editor for the IEEE Open Journal of Circuits and Systems and IEEE Solid-State Circuits Letters.

Date: 08/04/2024

Time: 14:00 – 15:30 Israel Time

Abstract:

This talk presents a focused overview of mm-wave power-amplifier (PA) designs in silicon, including design fundamentals, advanced PA architectures, and state-of-the-art design examples.

The talk will start with an introduction of PA performance metrics and their impacts on wireless systems. Next, it presents the design fundamentals of PA active devices and passive networks as well as power combining strategies.

The tutorial discusses advanced PA architectures, including Doherty, Outphasing, and Hybrid PAs, for high efficiency, linearity, and bandwidth. Further, advance and challenges of high mm-Wave PAs will be covered to address the emerging beyond-5G/6G applications. Finally, the talk will conclude with several state-of-the-art mm-wave PA design examples.

Bio:

Hua Wang is a full professor and chair of electronics at Department of Information Technology and Electrical Engineering (D-ITET) of Swiss Federal Institute of Technology Zürich (ETH Zürich). He is the director of the ETH Integrated Devices, Electronics, And Systems (IDEAS) Group. Prior to that, he was an associate professor with tenure at the School of Electrical and Computer Engineering (ECE) at Georgia Institute of Technology, USA. He held the Demetrius T. Paris professorship at School of ECE at Georgia Tech. He was the founding director of Georgia Tech Center of Circuits and Systems (CCS) and the director of the Georgia Tech Electronics and Micro-System (GEMS) lab. He worked at Intel Corporation and Skyworks Solutions from 2010 to 2011. He received his M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 2007 and 2009, respectively.

Dr. Wang is interested in innovating analog, mixed-signal, RF, and mm-Wave integrated circuits and hybrid systems for wireless communication, sensing, and bioelectronics applications. He has authored or co-authored over 200 peer-reviewed journal and conference papers.

Dr. Wang is an IEEE Fellow. He received the DARPA Director’s Fellowship Award in 2020 (the first awardee in Georgia Tech’s history), the DARPA Young Faculty Award in 2018, the National Science Foundation CAREER Award in 2015, the Qualcomm Faculty Award in 2020 and 2021, the IEEE MTT-S Outstanding Young Engineer Award in 2017, the Georgia Tech Sigma Xi Young Faculty Award in 2016, the Georgia Tech ECE Outstanding Junior Faculty Member Award in 2015, and the Lockheed Dean’s Excellence in Teaching Award in 2015.

His research group has won multiple academic awards and best paper awards, including the 2019 Marconi Society Paul Baran Young Scholar, the IEEE RFIC Best Student Paper Awards (2014, 2016, 2018, and 2021), the IEEE International Microwave Symposium (IMS) Best Student Paper Award 2021, the IEEE CICC Outstanding Student Paper Awards (2015, 2018, and 2019), the IEEE CICC Best Conference Paper Award (2017), the 2016 IEEE Microwave Magazine Best Paper Award, and the IEEE SENSORS Best Live Demo Award (2nd Place in 2016).

Dr. Wang is a Technical Program Committee (TPC) Member for IEEE ISSCC, RFIC, CICC, and BCICTS conferences. He is a Steering Committee Member for IEEE RFIC and CICC. He is the Conference Chair for CICC 2019 and Conference General Chair for CICC 2020. He is a Distinguished Microwave Lecturer (DML) for the IEEE Microwave Theory and Techniques Society (MTT-S) for the term of 2022-2024. He was a Distinguished Lecturer (DL) for the IEEE Solid-State Circuits Society (SSCS) for the term of 2018-2019. He was the Chair of the Atlanta’s IEEE CAS/SSCS joint chapter that won the IEEE SSCS Outstanding Chapter Award in 2014.

Date: 27/03/2024

Time: 16:00 – 17:30 Israel Time

Important: the webinar is free of charge but registration is required

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Abstract

Timing recovery techniques have evolved significantly over the last 25 years of high-speed link design. In the first decade, this evolution was motivated by technology scaling and scalability, where it gradually moved to a fully digital implementation from an analog PLL-based approach. However, the evolution in the last decade is motivated by the adoption of multilevel signaling. The emergence of MMSE as an alternative to 2X oversampled solutions is an example of such recent developments. This talk aims to bring designers up to speed on the state-of-the-art ADC-DSP solutions, explain their motivation, and finally conclude with silicon results to validate the performance improvement achievable in these architectures.

Biography

Masum Hossain (M’11) received the B.Sc. degree from the Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 2002, the M.Sc. degree from Queen’s University, Kingston, ON, Canada, in 2005, and the Ph.D. degree from the University of Toronto, Toronto, ON, in 2010. From 2007 to 2013, he worked in product development and industrial research, focusing on high-speed link design in multiple organizations, including Gennum and Rambus. In 2013, he joined the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada. Recently in 2023, he joined Carleton University in Ottawa, Canada. Dr. Hossain received the Best Student Paper Award at the 2008 IEEE Custom Integrated Circuits Conference and the Analog Device’s Outstanding Student Designer Award in 2010. In 2021 he received EPS society nominated best paper award in IEEE Transaction in Components, Packaging and Manufacturing.

Date: January 28, 2024, Sunday

Time: 17:00 – 18:30 Israel Time

Important: the webinar is free of charge but registration is required

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Abstract

Neural network (NN) models are rapidly increasing in size and complexity, surpassing the pace of NN chip upgrades. The development of monolithic chips to match these evolving models is both expensive and challenging. Alternatively, modular chiplets can be designed and reused to create multi-chip packages (MCPs) capable of addressing diverse NN models and tasks. The future success of chiplet technology hinges on advancements in chiplets that offer high utilization and flexibility, efficient high-bandwidth die-to-die interfaces, and high-density packaging. In this presentation, I will introduce two MCPs resulting from our collaboration with Intel and the Institute of Microelectronics in Singapore. The first MCP, NetFlex, integrates four NN chiplets using high-density fan-out wafer level packaging (HD-FOWLP). NetFlex’s flexible chiplet design and lightweight die-to-die interface enable scalability for larger configurations. The second MCP, Arvon, utilizes Embedded Multi-die Interconnect Bridge (EMIB) to integrate an FPGA chiplet and two DSP chiplets. Arvon is a programmable MCP that supports various workloads, including NN and communication signal processing. Its flexibility allows for scalability to accommodate evolving workloads over time.

Bio

Zhengya Zhang received the B.A.Sc. degree from the University of Waterloo in 2003, and the M.S. and Ph.D. degrees from UC Berkeley in 2005 and 2009, respectively. Since 2009, he has been with the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor, where he is currently a full professor. His research primarily focuses on low-power and high-performance VLSI circuits and systems, with applications in computing, communications, and signal processing. Dr. Zhang was a recipient of the NSF CAREER Award, the Intel Early Career Faculty Award, the University of Michigan Neil Van Eenam Memorial Award, and the David J. Sakrison Memorial Prize from UC Berkeley. He serves as an IEEE Solid-State Circuits Society Distinguished Lecturer.

Date: December 7th, 2023

Time: 16:00 Israel Time

Important: participation is free of charge, but registration is required

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Abstract

This talk will cover practical challenges for cryogenic CMOS designs for next
generation quantum computing. Starting from system level, it will detail the design considerations
for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in
14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital
processor that supports waveform generation and phase rotation operations combined with a low
power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform
generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control
signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal
bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected
to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence
times were 75.5μS and 73μS, respectively, in each case comparable to results achieved using
conventional room temperature controls. In further tests with transmons, a qubit-limited error rate
of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room
temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation
per qubit under active control is 23mW.

Biography

Sudipto Chakraborty received his B. Tech from Indian Institute of Technology,
Kharagpur in 1998 and Ph.D in EE from Georgia Institute of Technology in 2002. He worked as
a researcher in Georgia Electronic Design Center (GEDC) till 2004. From 2004 to 2016, he was
a senior member of technical staff at Texas Instruments where he contributed to low power
integrated circuit design in more than 10 product families in the areas of automotive, wireless,
medical and microcontrollers. Since 2017, he has been working at the IBM T. J. Watson
Research Center where he leads the low power circuit design for next generation quantum
computing applications using nano CMOS technology nodes. He has authored or co-authored
more than 75 papers, two books and holds 87 US patents. He has served in the technical program
committees of various conferences including CICC, RFIC, IMS and has been elected as an IBM
master inventor in 2022 for his contributions.

Date & Time: Tuesday, November 28, 2023 from 17:00 – 18:30 Israel Time

Important: participation is free of charge but registration is required

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Abstract 

Microwave and Millimeter-wave switches are key components in communication systems. They are used for signal routing and for realizing a wide range of reconfigurable microwave and millimeter-wave devices.  Phase Change Materials (PCM) have been widely used in optical storage media and non-volatile memory device applications. Over the past recent years, there have been interest in exploiting the PCM materials such as germanium telluride (GeTe) and metal insulator transition materials such as vanadium oxides (VO2) for RF applications. The principle of operation of PCM devices is based on the ability of the material to transform from a high-resistivity state (amorphous phase) to a low-resistivity state (crystalline phase) and vice versa with the application of short duration pulses.  Several orders of magnitude in resistivity change can be achieved by PCM technology allowing the realization of highly miniature microwave and millimeter-wave switches.  In addition to miniaturization, GeTe based switches offer latching functionality and ease of monolithic integration with other RF circuits. This talk will address recent developments in PCM switches and their applications to the realization of   reconfigurable filters, switch matrices, phase shifters, variable attenuators, and reflective intelligent surfaces. It outlines major design considerations for tunable filters presenting techniques to realize tunable filters that maintain filter performance over tuning range, illustrating examples of tunable filters tuned only a by single tuning element. The talk also addresses existing tuning technologies, providing a comparison between Semiconductor, MEMS and PCM tuning elements in terms of linearity, insertion loss, suitability for use at millimeter-wave frequencies and ease of integration with high-Q filters. Very recent results for PCM-based reconfigurable acoustic filters are also presented.

Biography

Raafat Mansour is a Professor of Electrical and Computer Engineering at the University of Waterloo and holds Tier 1 – Canada Research Chair (CRC) in Micro-Nano Integrated RF Systems. He held an NSERC Industrial Research Chair (IRC) for two terms (2001-2005) and (2006-2010). Prior to joining the University of Waterloo in January 2000, Dr. Mansour was with COM DEV Cambridge, Ontario, over the period 1986-1999, where he held various technical and management positions in COM DEV’s Corporate R&D Department. Professor Mansour holds 44 US and Canadian patents and more than 420 refereed IEEE publications to his credit. He is a co-author of a 23-chapter Book published by Wiley and has contributed 7 chapters to five other books.  Professor Mansour founded the Centre for Integrated RF Engineering (CIRFE) at the University of Waterloo https://uwaterloo.ca/centre-integrated-rf-engineering/.  It houses a clean room and a state-of-the-art RF test and characterization laboratory.  He was as the Technical Program Chair of the 2012 IEEE International Microwave Symposium (IMS).   Professor Mansour is a Fellow of the IEEE, a Fellow of the Canadian Academy of Engineering (CAE), a Fellow of the Engineering Institute of Canada (EIC).  He was the recipient of the 2014 Professional Engineers Ontario (PEO) Engineering Medal for Research and Development and the 2019 IEEE Canada A.G.L. McNaughton Gold Medal Award.

Date: Thursday, February 29, 2024

Time: 16:00 Israel Time

Important: Participation is free of charge but registration is required.

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Abstract

Both video compression and computer vision make use of spatial and temporal patterns present in images. With the rise of the internet of video things, numerous opportunities have arisen for synergizing AI and video compression. In this presentation, we will explore two main aspects. Firstly, we’ll delve into utilizing compressed data to perform AI tasks. Secondly, we’ll dive into harnessing AI for video compression and image signal processing.

Bio

Yen-Kuang Chen received his Ph.D. degree from Princeton University. His research areas span from emerging applications that can utilize the true potential of multimedia and Internet of Things (IoT) to computer architecture that can embrace emerging applications. He has 100+ patents and 100+ technical publications. He is recognized as an IEEE Fellow for his contributions to algorithm-architecture co-design for multimedia signal processing.

Important: participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website