Chiplet approaches to scale up and scale out machine learning computation


Neural network (NN) models are rapidly increasing in size and complexity, surpassing the pace of NN chip upgrades. The development of monolithic chips to match these evolving models is both expensive and challenging. Alternatively, modular chiplets can be designed and reused to create multi-chip packages (MCPs) capable of addressing diverse NN models and tasks. The future success of chiplet technology hinges on advancements in chiplets that offer high utilization and flexibility, efficient high-bandwidth die-to-die interfaces, and high-density packaging. In this presentation, I will introduce two MCPs resulting from our collaboration with Intel and the Institute of Microelectronics in Singapore. The first MCP, NetFlex, integrates four NN chiplets using high-density fan-out wafer level packaging (HD-FOWLP). NetFlex’s flexible chiplet design and lightweight die-to-die interface enable scalability for larger configurations. The second MCP, Arvon, utilizes Embedded Multi-die Interconnect Bridge (EMIB) to integrate an FPGA chiplet and two DSP chiplets. Arvon is a programmable MCP that supports various workloads, including NN and communication signal processing. Its flexibility allows for scalability to accommodate evolving workloads over time.


Zhengya Zhang received the B.A.Sc. degree from the University of Waterloo in 2003, and the M.S. and Ph.D. degrees from UC Berkeley in 2005 and 2009, respectively. Since 2009, he has been with the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor, where he is currently a full professor. His research primarily focuses on low-power and high-performance VLSI circuits and systems, with applications in computing, communications, and signal processing. Dr. Zhang was a recipient of the NSF CAREER Award, the Intel Early Career Faculty Award, the University of Michigan Neil Van Eenam Memorial Award, and the David J. Sakrison Memorial Prize from UC Berkeley. He serves as an IEEE Solid-State Circuits Society Distinguished Lecturer.

Date: December 7th, 2023

Time: 16:00 Israel Time

Important: participation is free of charge, but registration is required

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