Crossbar based Mixed-Signal Neural Architectures under Variability and Parasitics

Abstract 

In this lecture, the variability impact, compensation techniques, and variability-aware neural architectures are discussed. Variability and paracitics pose significant challenges in ensuring accurate multiply and accumulate (MAC) computations emulated with a crossbar. In most neural networks, the MAC forms the core computing module to implement a neuron and, consequently, neural networks. The analog MAC blocks are particularly susceptible to variability and parasitics, which can result in inaccuracies in the computation process. Therefore, developing techniques to mitigate these challenges is crucial for the successful implementation of variability averse mixed-signal neural architectures.

Bio

Alex James is the dean of academics and full-professor of AI hardware at Digital University Kerala; and CTO of India Graphene and Engineering Innovation Centre (a section 8 company). James received his PhD from Queensland Micro and Nanotechnology Centre, Griffith University, Australia. He heads the Maker Village, one of the largest electronic hardware incubators in India with over 80 electronics startups. He heads the Centre for excellence in Intelligent IoT Sensors, and India Innovation Centre for Graphene. He is the founding director board member of India’s first Digital Science Park. He has spun out multiple startup companies from his research group; published more than 200 papers. For the last two decades, he worked in the areas of board design, signal integrity and mixed signal design in Industry and in the area of AI hardware and systems in academia. He has taught more than 60 courses, in the areas of chip design and AI. He was an associate editor for IEEE TCAS1 (2018-2023), and IEEE OJCAS (2023).   He got the IEEE Kerala Section Best Researcher Award (2022), IEEE CASS Best Associate Editor for IEEE TCAS1 (2020-2021), Kerala State Higher Education Council Award 2022 – Kairali Gaveshana Puraskaram from the Kerala government, and 2024 IEEE Transactions on Circuits and Systems Guillemin-Cauer Best Paper Award.  First chair of IEEE CASS Kerala, which won the 2023 IEEE Circuits and Systems Regional Chapter-of-the-Year Award: Region 10 and 2024 IEEE Circuits and Systems Global Chapter-of-the-Year Award.  He is a member of SIG AgriFood and IEEE CASS Technical Committees on Nonlinear Circuits and Systems, Nonlinear Circuits and Systems Technical Committee (NCAS TC), Cellular Nanoscale Networks, and Memristor Array Computing. He is Associate Editor in Chief of IEEE Open Journal of Circuits and Systems (2024-2025) and Associate Editor of IEEE Access, Frontiers in Neuroscience, IEEE Transactions on Biomedical Circuits and Systems and IEEE Transactions on Circuits and Systems for Artificial Intelligence. He is an IET, BCS, and HEA Senior Fellow.

Date & Time: July 22, 2024, 11:00 – 12:30 Israel Time

Important: The webinar is free but registration is required. Register here

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Entrepreneurship in Semiconductors: Shai Cohen – The future? Hardware! A Personal Journey

Shai Cohen

The future? Hardware! A Personal Journey

Join Shai Cohen, co founder of Mellanox and proteanTecs on a fascinating journey through the dynamic world of hardware engineering and entrepreneurship In this presentation, Shai will describe the milestones of his career alongside significant advancements in the chip industry, from the early days of the personal computing revolution, through the flourishing of the server farm industry, IoT, and AI, to the advanced innovations of today and tomorrow Through stories from his experience at Intel, founding Mellanox, and leading proteanTecs Shai will demonstrate how engineering innovation and entrepreneurship are changing our world Join this talk to learn how you can lead and make an impact through hardware.

Shai Cohen, co-founder of Mellanox and proteanTecs is a seasoned entrepreneur in the chip industry with extensive experience in managing and building tech companies from their inception Since 2017 he has served as the CEO of proteanTecs a pioneer of deep data analytics for monitoring the health of electronic systems throughout their lifecycle, from manufacturing stages to ongoing market use Before founding proteanTecs Shai co founder of Mellanox, a global leader in InfiniBand and Ethernet technologies for high speed data transfer between servers and storage systems, a company later acquired by Nvidia As COO of Mellanox, he oversaw all operational and manufacturing functions and led research and development activities His professional journey began at Intel, where he was a senior team member in the Pentium processors department and a circuit design manager in the storage controllers group Shai holds a Bachelor’s degree in Electrical Engineering with honors from the Technion Israel Institute of Technology

Date: July 3, 2024, Wednesday

Time: 12:30 – 14:30 Israel Time

Location: 1003 Meyer Building

Register Here

ACRC 2024 Research Day

Calling all members of the Israeli computer hardware community!

The Architectures & Circuit Research Center (ACRC) invites you to a day of exploration, networking, and collaboration at our ACRC Research Day on July 1st, 2024.

 Register Here

Agenda:

16:00    Gathering

16:15    Greeting

16:20    Academia-Industry Panel, hosted by Prof. Avinoam Kolodny

    Topic: How AI/ML is Affecting Computer Hardware Development and What Can We Expect in the Future?

    Participants:       

        Prof. Shahar Kvatinsky, ECE Technion

        Rony Friedman, Apple

        Ofri Wechsler, Google

        Shlomit WeissFormer Intel

        Dr. Ofer Shacham – Majestic Labs

        Michael Kagan, NVIDIA

 

17:05     ACRC Award Ceremony

    Celebrate excellence! We will be recognizing the outstanding research achievements of graduate students.

 

17:20     Apple’s Tape-out Project Award Ceremony

    Applaud the brilliance of the next generation!

 

17:30     Graduate Student Research Poster Display

    Engage with the future of hardware innovation! Interact with graduate students from various Israeli universities and explore their cutting-edge research through interactive poster displays.

This event presents a unique opportunity to:

  • Gain insights into the latest advancements at the intersection of AI and computer hardware.
  • Network with fellow professionals from academia and industry.
  • Discover promising new research directions pursued by talented graduate students.
  • Foster collaborations that pave the way for groundbreaking developments in computer hardware.

Don’t miss this chance to connect, learn, and shape the future of computer hardware!

RSVP:

For registration and further details about the event schedule and location –  register here

We look forward to seeing you there!

Target Audience:

This invitation is extended to all researchers, engineers, students, and professionals with an interest in computer hardware in Israel.

 Register Here

NAND Storage – Overview, Challenges and Future Outlook

Biography

Dr. Assaf Shappir, a Talpiot graduate, received his B.Sc. degree in physics and mathematics from the Hebrew University of Jerusalem, Israel, in 1993 and M.Sc. and Ph.D. degrees in electrical engineering (physical electronics) from the Tel Aviv University, Israel, in 1999 and 2004 respectively. The Ph.D. thesis focused on redistribution of localized trapped charge in the oxide–nitride–oxide gate dielectric stack of the NROM nonvolatile memory device.
Dr. Shappir is a semiconductor veteran with over two decades in the Industry, including in Saifun Semiconductors, where he reached the position of Vice President of Technology Development, Intel and Apple. 

 Dr. Shappir has published 9 scientific papers, 21 conference papers, coauthored 2 book chapters and received 32 patents to date. 

Abstract

Demand for fast storage is growing at an exponential rate, with solid state non-volatile memory (NVM) being the only viable solution. System memory architecture is based on the principle of locality, with frequently accessed data being kept closest to the CPU and a trade-off in cost-performance is practiced using the various memory technologies. NAND Flash is unrivaled in the fast mass storage domain and thus, together with DRAM, has become an entrenched technology. 

In this talk I will review NAND Flash memory, from the underling physics of the basic memory cell, through array operation and the dominant reliability mechanisms. Next I will introduce 3D NAND, where memory cells are vertically stacked on top of each other, enabling a continuous density increase, as required to meet the growing market demand. Finally I will review NAND challenges and their storage system solutions,  including the use of error correction codes (ECC), as well as memory signal processing (MSP) techniques and memory management and redundancy schemes. My talk will conclude with a future outlook and the challenges ahead. 

Date: 02/06/2024

Time: 16:00 – 17:30 Israel Time

Important: The webinar is free but registration is required. Register here

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100-300 GHz Wireless: transistors, ICs, systems

Biography

Mark Rodwell holds the Doluca Family Endowed Chair in Electrical and Computer Engineering at UCSB and directs the SRC/DARPA Center for Converged TeraHertz Communications and Sensing. His research group develops nm and THz transistors, and high-frequency integrated circuits and systems. Prof. Rodwell received the 2010 IEEE Sarnoff Award, the 2012 Marconi Prize Paper Award, the 1997 IEEE Microwave Prize, the 2009 IEEE IPRM Conference Award, and the 1998 European Microwave Conference Microwave Prize.

Abstract

We describe the opportunities, and the research challenges, presented in the development of 100-300GHz wireless communications and imaging systems. In such links, short wavelengths permit massive spatial multiplexing both for network nodes and point-point links, permitting aggregate transmission capacities approaching 1Tb/s. 100-300GHz radar imaging systems can provide thousands of image pixels and sub-degree angular resolution from small apertures, supporting foul-weather driving and aviation. Challenges include the mm-wave IC designs, the physical design of the front-end modules, the complexity of the back-end digital beamformer required for spatial multiplexing, and, for imaging, the development of system architectures requiring far fewer RF channels than the number of image pixels. We will describe transistor development, IC design, and system design, and describe our efforts to develop 140GHz massive MIMO wireless hubs, and 210GHz and 280GHz MIMO backhaul links.

Date: 08/05/2024

Time: 17:00 – 18:30 Israel Time

Important: The webinar is free but registration is required. Register here

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An Overview on Interface Circuits and MPPT for Piezoelectric Energy Harvesting

Abstract: 

Piezoelectric vibration-to-electricity conversion provides a feasible solution to self-sustainability due to its relatively high power density, wider voltage range, and the compatibility with IC technology. In the past decade, we have seen a booming of various interface circuits developed for piezoelectric energy harvesting. The drastic difference between the operating speed of integrated circuits and mechanical vibrations provides a perfect venue for performing nonlinear switching and control in the interface operation with low power, allowing orders of magnitude of improvement in power extracting ability.

This tutorial will cover a wide range of state-of-the-art interface designs and MPPT methods for piezoelectric energy harvesting, while emphasizing the circuit implementation considerations. Specifically, after describing the basic full-bridge and half-bridge rectifiers, the Synchronized-Switch-Harvesting (SSH) technique that is the foundation of all modern nonlinear interface circuits will be introduced. Two major categories, namely, the open-circuit and the short-circuit structures, are then discussed in details. After that, the common MPPT algorithms and implementations will be reviewed. This talk will also cover topics such as non-resonant operations and multiple-input piezoelectric energy harvesting systems.

Bio: 

Ping-Hsuan Hsieh received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, Los Angeles, CA, in 2004 and 2009, respectively. From 2009 to 2011, she was with the IBM T.J. Watson Research Center, Yorktown Heights, NY. In 2011 she joined the Electrical Engineering Department of National Tsing Hua University, Hsinchu, Taiwan, where she is currently an Associate Professor. Her research interests focus on mixed-signal integrated circuit designs for high-speed electrical data communications, clocking and synchronization systems, and energy-harvesting systems.

Prof. Hsieh served in the Technical Program Committee of the IEEE International Solid-State Circuits Conference, and is currently a member of the Technical Program Committees of the IEEE Asian Solid-State Circuits Conference and the IEEE Custom Integrated Circuits Conference. She served as an Associate Editor for the IEEE Internet of Things Journal from 2014 to 2018, a Guest Editor for the IEEE Journal of Solid-State Circuits Special Issue in 2021, and is currently an Associate Editor for the IEEE Open Journal of Circuits and Systems and IEEE Solid-State Circuits Letters.

Date: 08/04/2024

Time: 14:00 – 15:30 Israel Time

Important: the webinar is free of charge but registration is required

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Fundamentals of RF and MM-Wave Power Amplifier Designs

Abstract:

This talk presents a focused overview of mm-wave power-amplifier (PA) designs in silicon, including design fundamentals, advanced PA architectures, and state-of-the-art design examples.

The talk will start with an introduction of PA performance metrics and their impacts on wireless systems. Next, it presents the design fundamentals of PA active devices and passive networks as well as power combining strategies.

The tutorial discusses advanced PA architectures, including Doherty, Outphasing, and Hybrid PAs, for high efficiency, linearity, and bandwidth. Further, advance and challenges of high mm-Wave PAs will be covered to address the emerging beyond-5G/6G applications. Finally, the talk will conclude with several state-of-the-art mm-wave PA design examples.

Bio:

Hua Wang is a full professor and chair of electronics at Department of Information Technology and Electrical Engineering (D-ITET) of Swiss Federal Institute of Technology Zürich (ETH Zürich). He is the director of the ETH Integrated Devices, Electronics, And Systems (IDEAS) Group. Prior to that, he was an associate professor with tenure at the School of Electrical and Computer Engineering (ECE) at Georgia Institute of Technology, USA. He held the Demetrius T. Paris professorship at School of ECE at Georgia Tech. He was the founding director of Georgia Tech Center of Circuits and Systems (CCS) and the director of the Georgia Tech Electronics and Micro-System (GEMS) lab. He worked at Intel Corporation and Skyworks Solutions from 2010 to 2011. He received his M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology, Pasadena, in 2007 and 2009, respectively.

Dr. Wang is interested in innovating analog, mixed-signal, RF, and mm-Wave integrated circuits and hybrid systems for wireless communication, sensing, and bioelectronics applications. He has authored or co-authored over 200 peer-reviewed journal and conference papers.

Dr. Wang is an IEEE Fellow. He received the DARPA Director’s Fellowship Award in 2020 (the first awardee in Georgia Tech’s history), the DARPA Young Faculty Award in 2018, the National Science Foundation CAREER Award in 2015, the Qualcomm Faculty Award in 2020 and 2021, the IEEE MTT-S Outstanding Young Engineer Award in 2017, the Georgia Tech Sigma Xi Young Faculty Award in 2016, the Georgia Tech ECE Outstanding Junior Faculty Member Award in 2015, and the Lockheed Dean’s Excellence in Teaching Award in 2015.

His research group has won multiple academic awards and best paper awards, including the 2019 Marconi Society Paul Baran Young Scholar, the IEEE RFIC Best Student Paper Awards (2014, 2016, 2018, and 2021), the IEEE International Microwave Symposium (IMS) Best Student Paper Award 2021, the IEEE CICC Outstanding Student Paper Awards (2015, 2018, and 2019), the IEEE CICC Best Conference Paper Award (2017), the 2016 IEEE Microwave Magazine Best Paper Award, and the IEEE SENSORS Best Live Demo Award (2nd Place in 2016).

Dr. Wang is a Technical Program Committee (TPC) Member for IEEE ISSCC, RFIC, CICC, and BCICTS conferences. He is a Steering Committee Member for IEEE RFIC and CICC. He is the Conference Chair for CICC 2019 and Conference General Chair for CICC 2020. He is a Distinguished Microwave Lecturer (DML) for the IEEE Microwave Theory and Techniques Society (MTT-S) for the term of 2022-2024. He was a Distinguished Lecturer (DL) for the IEEE Solid-State Circuits Society (SSCS) for the term of 2018-2019. He was the Chair of the Atlanta’s IEEE CAS/SSCS joint chapter that won the IEEE SSCS Outstanding Chapter Award in 2014.

Date: 27/03/2024

Time: 16:00 – 17:30 Israel Time

Important: the webinar is free of charge but registration is required

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Evolution of the Timing Recovery techniques in High-speed Links

Abstract

Timing recovery techniques have evolved significantly over the last 25 years of high-speed link design. In the first decade, this evolution was motivated by technology scaling and scalability, where it gradually moved to a fully digital implementation from an analog PLL-based approach. However, the evolution in the last decade is motivated by the adoption of multilevel signaling. The emergence of MMSE as an alternative to 2X oversampled solutions is an example of such recent developments. This talk aims to bring designers up to speed on the state-of-the-art ADC-DSP solutions, explain their motivation, and finally conclude with silicon results to validate the performance improvement achievable in these architectures.

Biography

Masum Hossain (M’11) received the B.Sc. degree from the Bangladesh University of Engineering and Technology, Dhaka, Bangladesh, in 2002, the M.Sc. degree from Queen’s University, Kingston, ON, Canada, in 2005, and the Ph.D. degree from the University of Toronto, Toronto, ON, in 2010. From 2007 to 2013, he worked in product development and industrial research, focusing on high-speed link design in multiple organizations, including Gennum and Rambus. In 2013, he joined the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada. Recently in 2023, he joined Carleton University in Ottawa, Canada. Dr. Hossain received the Best Student Paper Award at the 2008 IEEE Custom Integrated Circuits Conference and the Analog Device’s Outstanding Student Designer Award in 2010. In 2021 he received EPS society nominated best paper award in IEEE Transaction in Components, Packaging and Manufacturing.

Date: January 28, 2024, Sunday

Time: 17:00 – 18:30 Israel Time

Important: the webinar is free of charge but registration is required

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Chiplet approaches to scale up and scale out machine learning computation

Abstract

Neural network (NN) models are rapidly increasing in size and complexity, surpassing the pace of NN chip upgrades. The development of monolithic chips to match these evolving models is both expensive and challenging. Alternatively, modular chiplets can be designed and reused to create multi-chip packages (MCPs) capable of addressing diverse NN models and tasks. The future success of chiplet technology hinges on advancements in chiplets that offer high utilization and flexibility, efficient high-bandwidth die-to-die interfaces, and high-density packaging. In this presentation, I will introduce two MCPs resulting from our collaboration with Intel and the Institute of Microelectronics in Singapore. The first MCP, NetFlex, integrates four NN chiplets using high-density fan-out wafer level packaging (HD-FOWLP). NetFlex’s flexible chiplet design and lightweight die-to-die interface enable scalability for larger configurations. The second MCP, Arvon, utilizes Embedded Multi-die Interconnect Bridge (EMIB) to integrate an FPGA chiplet and two DSP chiplets. Arvon is a programmable MCP that supports various workloads, including NN and communication signal processing. Its flexibility allows for scalability to accommodate evolving workloads over time.

Bio

Zhengya Zhang received the B.A.Sc. degree from the University of Waterloo in 2003, and the M.S. and Ph.D. degrees from UC Berkeley in 2005 and 2009, respectively. Since 2009, he has been with the Department of Electrical Engineering and Computer Science at the University of Michigan, Ann Arbor, where he is currently a full professor. His research primarily focuses on low-power and high-performance VLSI circuits and systems, with applications in computing, communications, and signal processing. Dr. Zhang was a recipient of the NSF CAREER Award, the Intel Early Career Faculty Award, the University of Michigan Neil Van Eenam Memorial Award, and the David J. Sakrison Memorial Prize from UC Berkeley. He serves as an IEEE Solid-State Circuits Society Distinguished Lecturer.

Date: December 7th, 2023

Time: 16:00 Israel Time

Important: participation is free of charge, but registration is required

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Low power cryo-CMOS design for quantum computing applications

Abstract

This talk will cover practical challenges for cryogenic CMOS designs for next
generation quantum computing. Starting from system level, it will detail the design considerations
for a non-multiplexed, semi-autonomous, transmon qubit state controller (QSC) implemented in
14nm CMOS FinFET technology. The QSC includes an augmented general-purpose digital
processor that supports waveform generation and phase rotation operations combined with a low
power current-mode single sideband upconversion I/Q mixer-based RF arbitrary waveform
generator (AWG). Implemented in 14nm CMOS FinFET technology, the QSC generates control
signals in its target 4.5GHz to 5.5 GHz frequency range, achieving an SFDR > 50dB for a signal
bandwidth of 500MHz. With the controller operating in the 4K stage of a cryostat and connected
to a transmon qubit in the cryostat’s millikelvin stage, measured transmon T1 and T2 coherence
times were 75.5μS and 73μS, respectively, in each case comparable to results achieved using
conventional room temperature controls. In further tests with transmons, a qubit-limited error rate
of 7.76×10-4 per Clifford gate is achieved, again comparable to results achieved using room
temperature controls. The QSC’s maximum RF output power is -18 dBm, and power dissipation
per qubit under active control is 23mW.

Biography

Sudipto Chakraborty received his B. Tech from Indian Institute of Technology,
Kharagpur in 1998 and Ph.D in EE from Georgia Institute of Technology in 2002. He worked as
a researcher in Georgia Electronic Design Center (GEDC) till 2004. From 2004 to 2016, he was
a senior member of technical staff at Texas Instruments where he contributed to low power
integrated circuit design in more than 10 product families in the areas of automotive, wireless,
medical and microcontrollers. Since 2017, he has been working at the IBM T. J. Watson
Research Center where he leads the low power circuit design for next generation quantum
computing applications using nano CMOS technology nodes. He has authored or co-authored
more than 75 papers, two books and holds 87 US patents. He has served in the technical program
committees of various conferences including CICC, RFIC, IMS and has been elected as an IBM
master inventor in 2022 for his contributions.

Date & Time: Tuesday, November 28, 2023 from 17:00 – 18:30 Israel Time

Important: participation is free of charge but registration is required

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