On-chip communication directly impacts the performance, energy efficiency, and area of systems-on-chip, multi-processors, and highly-parallel accelerators, especially for emerging machine learning applications. In this talk, I will introduce a range of design options for on-chip interconnects, from point-to-point links to complex network topologies, starting from architecture to low-level circuit techniques. The presentation addresses base routing schemes and mapping of different protocol families, then moving on to microarchitecture, it presents flow-control and arbitration requirements and options. I will then detail circuit-level considerations, with a focus on different synchronization strategies across multiple clock domains, including multi-synchronous, source-synchronous-clocking, and fully-asynchronous circuits.

Yvain Thonnart received the MS degree from Ecole Polytechnique and an engineering diploma from Telecom Paris, France in 2005. He then joined the Technological Research Division of CEA, the French French Alternative Energies and Atomic Energy Commission, within the CEA-Leti institute until 2019, then within the CEA-List institute. He has led the development of several large research projects for on-chip communications, focusing on the maturation of novel concepts towards industrial adoption, such as communication between multiple voltage and frequency domains, 3D-stacked circuits, and optical on-chip interconnects, leading to more than 70 publications and 10 patents. He is now senior expert on communication and synchronization in systems on chip, and scientific advisor for the mixed-signal design lab. His main research interests include asynchronous logic, networks on chip, physical implementation, emerging technologies integration such as photonics, cryoelectronics and interposers. He is currently serving in the technical program committee of the ISSCC.

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46954 – Accuracy Improvement of the Analog Integrated Circuits

February 26-28/2023, 9:00 a.m.

Auditorium 1003, Meyer Bld

Dr. Vadim Ivanov, Texas Instruments

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*Registration is open until February 20, 2023

Course Content:

In 1951 Bernard Tellegen proved that set of an ideal amplifier, reference, limiter, and RC network
is functionally sufficient for the implementation of any analog functions. It has started a neverending quest to design ideal amplifiers and references. The most accurate voltage references use
the bandgap voltage of the silicon. Out of many options, the de facto standard of an ideal amplifier
is an operational amplifier. Operational amplifiers and bandgap voltage references have been the
first analog ICs in production (since the 1960-s), now with >20,000 types of such ICs available
from almost every semiconductor company and enjoying multi-billion sales just for stand-alone
ICs.
This course will start with an overview of the analog design methodology based on feedback
control of every important parameter in the system. While every feedback loop may be unstable,
we will demonstrate ways to verify and guarantee the stability of the resulting multiloop system.
This methodology will be illustrated with multiple non-trivial examples of current mirrors with
unmeasurable high output impedance; transconductors with wide input range, any load-stable
LDOs with instant load regulation.
Based on this methodology, we will proceed with the in-depth design of the bandgap voltage
references in different processes and for different applications. We will consider embedded
references in digital systems, references for the highest state-of-the-art accuracy, and references
with nanopower consumption. In addition to the circuit design and tradeoffs between
noise/consumption/settling time, we will discuss the challenges with testing, trimming, and
packaging.
The next part of the course is dedicated to improving all OpAmp parameters. These include
speed-to-power ratio, noise, CMRR and PSRR, and input and output voltage range. We will
consider offset and offset temperature drift trimming as well as structures and circuits for offset
elimination by auto-zeroing and chopping.

Topics per Day:

Day 1 (4 academic hours): Structural design methodology and
practical frequency compensation
Discussed are the rules of generating circuit solutions with desired analog functionality out of an
immense variety of options. Design starts with a graphic presentation of the problem with signal
flow graphs or block diagrams, then changing it to the form where everything necessary is
controlled with a dedicated feedback loop, and, finally, implementing the structure using an
elementary cell library. The resulting circuit comprises multiple feedback loops. Interaction
between these loops makes frequency compensation of such a system non-trivial task,
unsupported by the general control theory. Every MOS or bipolar transistor is nonlinear, which
may cause conditional stability and complicated compensation.
We will consider system structure design for stability, and additional elementary circuit cells to
the textbook set, resulting in achieving unconditional system stability when component
parameters vary, and when load and signal source impedance is not well defined.
Examples include LDOs stable with any load capacitance, transconductors with wide (few volts)
input voltage range, and multistage operational amplifiers.
Day 2 morning (2 academic hours): Bandgap voltage references
Discussed are error sources of the bandgap voltage references and techniques for improving their
accuracy: circuit techniques for low-noise bandgap generation core, feedback amplifier with
chopping offset elimination, output buffer with mOhm output impedance and fast settling on load
changes; single- dual and triple temperature trimming; packaging requirements; testing and
application particulars. Also presented circuit solutions for reverse bandgap reference,
operational from 0.9V supply, and reference structure and implementations with nanoampere
consumption.
Day 2 afternoon and Day 3 (7 academic hours): Operational amplifier
speed, accuracy, and consumption improvement
Discussed are circuit techniques to improve all essential parameters of the Operational Amplifiers.
Most circuit techniques shown have been previously published only in patents and applications.
Examples include input stage design for low offset, noise, unmeasurable PSRR and CMRR, input
common-mode voltage range; ways of improvement OpAmp speed to power ratio; open loop
gain; power supply range both in high- and low-voltage amplifiers; improving offset by a packagelevel trimming, auto-zero, and chopping; achieving high capacitive drive capability; current limit,
temperature protection, POR.

Prerequisites:
044137 Electronic Circuits

Recommended prerequisites:
046187 Analog Circuits Design

Grading:

Written exam – 100%

Instructor’s Bio:

MSEE 1980, Ph.D. 1987, both in the USSR. Designed electronic
systems and ASICs for naval navigation equipment from 1980 to
1991 in St. Petersburg, Russia and mixed signal ASICs for sensors,
GPS/GLONASS receivers and for motor control between 1991 and
1995.
Joined Burr Brown, now Texas Instruments, Tucson, in 1996, where
worked on the operational, instrumentation, power amplifiers,
references and switching and linear voltage regulators, and where
he is currently the Operational Amplifier Technologist. Has 126 patents, with more pending, on
analog circuit techniques and authored > 30 technical papers and three books: “Power Integrated
Amplifiers” (Leningrad, Rumb, 1987), “Analog system design using ASICs” (Leningrad, Rumb,
1988), both in Russian, and “Operational Amplifier Speed and Accuracy Improvement”, Springer,
2004

For registration click here

*Registration is open until February 12, 2023

Biological processes such as neuronal signaling and cell growth are among the most complex micro- and nano-scale processes in nature. Historically such processes have been studied at the system level because there were no tools available to study individual components of the process. However, cellular-level interfacing is needed to provide a better understanding of the brain and to develop more advanced prosthetic devices and brain-machine interfaces. With semiconductor technology innovations, much recent work has been focused on unraveling biological complexity, but also on driving new diagnoses, treatments, and therapies that are tailored to the individual. One of the drivers behind those innovations is novel CMOS circuits enabling multi-modal, high-precision data collection and analysis at ultra-low power consumption. In this talk, I will present recent biomedical developments based on silicon technology, and I will discuss the requirements, materials, circuit techniques, and design challenges of their ASIC and SoC platforms.

Carolina Mora Lopez received her Ph.D. degree in Electrical Engineering in 2012 from the KU Leuven, Belgium, in collaboration with imec, Belgium. From 2012 to 2018, she worked at imec as a researcher and analog designer focused on interfaces for neural-sensing applications. During this time, she was the lead analog designer and project leader of the Neuropixels development project which resulted in the conception and fabrication of the Neuropixels 1.0 and 2.0 neural probes. She is currently the principal scientist and team leader of the Circuits & Systems for Neural Interfaces team at imec, which develops circuits and technologies for electrophysiology, neuroprosthetics and BMI. Her research interests include analog and mixed-signal circuit design for sensor, bioelectronic and neural interfaces. Carolina is a senior IEEE member and serves on the technical program committee of the ISSC conference, ISSCC SRP, VLSI circuits symposium, and ESSCIRC conference.

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We are heading to an exciting world where the boundaries between the physical world and the digital/virtual world are blurring, and opportunities and possibilities that are unseeable today will be unleashed. This fascinating future world requires drastic technological breakthroughs and innovations. One key requirement is immersive connectivity and sensing with everything. In this talk, I will present our group research activities in integrated circuits and systems advancing this mission in three key pillars: wireline communication/interconnect, sensing, and wireless communication and radar.

Dr. Qun Jane Gu received a Ph.D. from the University of California, Los Angeles in 2007. After a couple of years of industry experience, she started her academic career in 2010 at the University of Florida. Since 2012, she has been with the University of California, Davis, where she is currently a professor. Dr. Jane Gu’s group is passionate in high performance RF, mm-wave and THz integrated circuits and systems and its broad applications. The works from her group have won nine best paper awards from international conferences, including four times from IEEE MTT-S International Microwave Symposium (IMS). She has received 2013 NSF CAREER award, 2015 UC Davis Outstanding Junior Faculty Award, 2017 and 2018 Qualcomm Faculty Award, 2019 UC Davis Chancellor Fellow, and 2022-23 Solid-State Circuits Society Distinguished Lecturer. She is a TPC member of solid state conferences RFIC, CICC and ISSCC.

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A graph is a ubiquitous data structure that models entities and their interactions through the collections of nodes and edges. It is widely employed in several important application domains ranging from social media, navigation tools, search engines, physics simulations, and biology. Despite its prevalence, the performance of graph workloads on commercial platforms is limited. This is mainly due to the irregular nature of memory accesses and convoluted control flow instructions used in graph applications while accessing large amounts of real-world graph data (i.e., billions of nodes/edges). Therefore, there is a pressing need for optimizing the performance of graph workloads.

In this talk, I will present a systematic optimization study of graph workloads running on both static and dynamic graphs. Specifically, I will present two of my most recent works called NDMiner [ISCA 2022] and Mint [MICRO 2022] in detail. NDMiner optimizes the execution of the Graph Pattern Mining (GPM) application. In this work, I will showcase how to combine the benefits of Near Data Processing (NDP) and domain specialization to improve GPM workload performance. Mint, on the other hand, investigates and optimizes a pattern mining application on temporal graphs (a type of dynamic graph), called temporal motif mining. Mint presents a new programming model, hardware accelerator architecture, and domain-specific optimization to significantly improve the performance of mining temporal motifs. In addition to these works, I will briefly tough upon our optimization and detailed benchmarking effort for traditional graph processing algorithms (e.g., PageRank and SSSP) and random walk-based graph learning pipelines (e.g., node classification and link prediction).

Nishil Talati recently completed his PhD from University of Michigan, USA. Prior to joining the PhD program, he completed a master’s degree with thesis from Technion, Israel, and an undergraduate degree from BITS Pilani, India. Nishil’s research interests span computer architecture, compilers, and software engineering. Specifically, he has worked on several optimization efforts to improve the memory performance of modern computing systems. One of his recent works was recognized as the best paper award at HPCA 2021.

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I will discuss the challenge of using CMOS chips in optical communication applications in this talk. Optical communication has many advantages compared to copper and wireless systems. However, the optical-electrical conversion in the receiver typically requires an external photodiode adding volume and cost to the system. I will explain how it is possible to realize fully integrated optical receivers in CMOS using a pn-photodiode or a Schottky photodiode. While the former is only sensitive to 850 nm light, the latter is sensitive to the more abundant 1310 nm and 1550 nm wavelengths. Due to the intrinsically low response of these integrated photodiodes, low-noise readout circuits are required, which I will also discuss.

Filip Tavernier obtained the M.Sc. degree in Electrical Engineering and the Ph.D. degree in Engineering Science from KU Leuven, Leuven, Belgium, in 2005 and 2011, respectively. During 20112014, he was Senior Fellow in the microelectronics group at the European Organization for Nuclear Research (CERN) in Geneva, Switzerland. He was involved in chip designs for the upgrade program of the Large Hadron Collider (LHC) experiments. In 2014, he rejoined KU Leuven at the Department of Electrical Engineering (ESAT-MICAS). As of October 2015, he has been a professor within the same department. His main research interests include circuits for optical communication, data converters, DC-DC converters, and chips for cryogenic environments. Filip is a member of the technical program committees of ESSCIRC, CICC, and SBCCI. He has been SSC-L Guest Editor and is the current SSCS Webinar Chair.

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Michael Kagan is NVIDIA CTO (Chief Technology Officer) since May 2020. He joined NVIDIA through Mellanox acquisition.

Michael Kagan was previously Mellanox CTO and a co-founder of Mellanox that was founded in April 1999.

From 1983 to April 1999, Mr. Kagan held a number of architecture and design positions at Intel Corporation. While at Intel Corporation, Mr. Kagan was architect of the i860XP vector processor, managed Pentium MMX design, and managed the architecture team of the Basic PC product group.

Mr. Kagan holds a BSc. in Electrical Engineering from the Technion — Israel Institute of Technology.

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