| Instructor: | Dr. Eitan Shauly, Tower Semiconductor |
| Teaching Assistant: | TBD |
| Lectures: | 3 days |
| Academic Points: | 1 |
| Exam: | TBD |
| Course Fees: | 1700$ (See membership options) |
For registration, click here
Registration closes on March 04, 2025
Date: March 09 – 11, 2025
Time: 9:00 – 18:00
Course Content:
In this course, we will discuss systematically the various failure mechanisms that may occur during the manufacturing and use of the semiconductor devices: electromigration, stress-induced voids, Hot-Carrier Injection, Negative Bias-Temperature Instability, oxide wear out (breakdown, Time-Depended-Dielectric-Breakdown (TDDB), and Inter-Metal-Dielectric-TDDB), and others. We also discuss topics such as automotive reliability, ISO26262, wafer foundry qualification, and environmental reliability. The course provides an excellent opportunity to obtain first-level knowledge for individuals who already have some process background but are relatively new to semiconductor reliability.
The course will be in Hebrew, but all slides will be in English.
Course Outcomes:
Fulfilling course requirements student is expected to be able to:
- Understand the different reliability mechanisms in CMOS devices,
- Understand the dependencies between the process and the stress conditions in the field on the failure rate
- Fully characterize and analyze the reliability performance and figure of merits of different devices, by carful understanding the different mechanisms and the reliability characterization.
- Deep understanding of the way the semiconductor devices operates under stress (transistors, capacitors, resistors and more) thus how to optimize them to achieve the needed performance, with emphasize on reliability for automotive
Prerequisite: 044231 Electron Devices 1 (MOS)
Timetable :
| 09-Mar’25 | 1 | 09:00 ~ 09:50 | Course Introduction, Introduction to Reliability and time degradation, (TAF, CAF, VAF), modeling |
| 2 | 10:00 ~ 10:50 | Physical failure mechanisms: HCI, NBTI, EM, SM, GOI, ESD, others | |
| 3 | 11:00 ~ 12:00 | Electromigration: definition; Mass motion and flux modeling; Blech length; Void formation; Stress effects | |
| 4 | 12:00 ~ 13:00 | Lunch Break | |
| 5 | 13:00 ~ 13:50 | Electromigration – testing and qualification; | |
| 6 | 14:00 ~ 15:15 | Electromigration: Grain Size dependency, Alloys, Barrier metals and other process related performances improvement, N7 and N5 BEOL solutions | |
| 7 | 15:30 ~ 17:00 | Electromigration: LT as function of Width and length, AC vs DC conditions; EM scaling limitations. Stress Migration: Introduction |
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| 8 | 17:10 ~ 18:00 | Stress Migration: void formation and growth; SIV modeling; Layout solution, double via solution; Stacked via sensitivity, effect of misalignment | |
| 10-Mar’25 | 1 | 09:00 ~ 09:50 | Hot-Carrier-Injection: mechanism and modeling; DAHC (Drain Avalanche Hot carrier), CHE (Channel hot Electron), SHE (Substrate Hot Electron), others; Lucky Electron Model, |
| 2 | 10:00 ~ 10:50 | HCI: HCI degradation under worse case conditions in planar MOSFETs and FinFETs, qualification – measurement, analysis and modeling, Process solutions to reduce HCI: DDD, spacer with LDD implant, HALO/Pockets; Aging | |
| 3 | 11:00 ~ 12:00 | Negative-Bias-Temperature-Instability: Degradation Mechanism and modeling; Interface traps; The Reactive-Diffusion (R-D) degradation model, PBTI; | |
| 4 | 12:00 ~ 13:00 | Lunch Break | |
| 5 | 13:00 ~ 13:50 | NBTI: Stress time and degradation saturation; NBTI recovery; Dynamic NBTI; Qualification and modeling; Process dependency; Boron Penetration, ; Oxynitridization, DPN; Fluorine passivation, | |
| 6 | 14:00 ~ 15:15 | Gate Oxide Integrity: GOX scaling, interfaces, Leakage; Tunneling, TAT, Qbd, Vbd,; Layout sensitivity; | |
| 7 | 15:30 ~ 17:00 | GOI: Weibull distribution; Charge inside GOX, C-V; TDDB – physical mechanisms, IBM modeling, | |
| 8 | 17:10 ~ 18:00 | GOI / Tirgol | |
| 11-Mar’25 | 1 | 09:00 ~ 09:50 | GOI: Process Enhancement GOI; Oxide-Nitride-Oxide, Nitride, Ta2O5; HKMG (Hf-based); |
| 2 | 10:00 ~ 10:50 | GOI: TDDB of FinFETs, TDDB – Qualification and Modeling, IMD-TDDB | |
| 3 | 11:00 ~ 12:00 | Plasma Induced Damage: The mechanism of PID; Plasma non-uniformity, shading, Antenna Ratio: traditional definition; Antenna rules, calculations and examples; Limitation of the traditional ratio; Cumulative plasma damage; Protection: bridging, protective diode; Well charging, protection | |
| 4 | 12:00 ~ 13:00 | Lunch Break | |
| 5 | 13:00 ~ 13:50 | Technology qualification: TEG, TQV, ELFR, Burn-In, HTOL, THB, 85/85 | |
| 6 | 14:00 ~ 15:15 | Technology qualification: TMCL, JEDEC JP001 | |
| 7 | 15:30 ~ 17:00 | Automotive: Reliability, AEC-Q100, ZEVI, Mission Profile, Quality, IARF16949, DFA, IPs, ISO 26262 | |
| 8 | 17:10 ~ 18:00 | Electrostatics Discharge: Mechanism, examples for failures, Prevention and protection, HBM, MM, CDM |
Lecturer: Dr. Eitan Shauly, Tower Semiconductor
Bio:
Eitan N. Shauly received the B.Sc. degree in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, in 1989, and M.Sc. and Ph.D. degrees in materials engineering from the Technicon — Institute of Technology, Haifa, in 1995 and 2001, respectively. He has worked for Tower Semiconductor since 1989. During 1989–1994 he was a diffusion and ion implantation engineer. During 1994–1997 he was a device/Integration engineer, focusing on process integration and process modeling. Since 1998 he is doing integration, focusing on platform development, design rules, Design-for-Manufacturing and Automotive. Dr. Shauly is also teaching at the faculty of Material Engineering, Technicon Haifa, courses related to VLSI technology: “VLSI processing” and “CMOS Devices and Integration”.
Registration closes on March 04, 2025
For registration, click here