Speaker: Aviv Ronen from Rafael ltd

Date: Wednesday, December 2, 2026

Time: 16:00 – 17:30 Israel Time

Language: English

Location: Zoom Session

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Abstract:

For decades, chip design followed a linear workflow: electrical engineers designed the silicon, and only when tape-out approached was the IC handed over for packaging. Today, with the rise of high-power density, high-speed signals, and 2.5D/3D integration, treating packaging as an afterthought is a recipe for project failure.

This lecture highlights the critical need for early-stage integration between chip designers and packaging/microelectronic assembly engineers. Aimed at electrical engineers, this session will demonstrate how physical, thermal, and mechanical packaging constraints directly govern electrical performance—from power integrity and parasitics to thermomechanical stress and yield. Whether you are designing – digital ICs, RF components, or power management circuits – understanding why packaging engineers belong at the architecture table from Day One will change how you approach system-level design.

Bio:

Aviv serves as the Chief Technology Officer at Beckermus Technologies, where he bridges deep technical authority with commercial and strategic leadership. He holds a degree in Mechanical Engineering from the Technion – Israel Institute of Technology and brings over 23 years of specialized experience from his tenure in the Micro-Systems Department at Rafael.

As the technical voice of Beckermus, Aviv drives innovation in microelectronics, high-density semiconductor packaging, electro-optics, and materials science. Utilizing extensive expertise in precision CAD, thermal management, and advanced assembly workflows, he guides complex electro-optical concepts from early-stage architecture through to high-reliability, scalable manufacturing.

In addition to directing technology development and client acquisition, Aviv plays a prominent role in the broader engineering community. He currently serves as the Chairman of the IEEE EPS Israel Chapter and Chairman of the Electronic & Microelectronic Packaging Branch at the Association of Engineers, Architects and Academics in Technological Sciences in Israel (AEAI). Combining decades of defense-grade engineering experience with industry leadership, Aviv drives cutting-edge packaging solutions across demanding high-tech markets.

The webinar is free but registration is required!

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Speaker: Prof. Alon Ascoli, Politecnico di Torino, Turin, Italy

Date: Thursday, December 24, 2026

Time: 12:00 – 13:30 Israel Time

Language: English

Location: Room 506, Zisapel Building, Technion Haifa.

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Abstract:

In this talk, we employ a novel analysis approach, based upon frequency-domain methods,
which are typically employed in Control Theory [1], to explore the origin for Turing Instabilities [2] in Reaction-Diffusion Cellular Neural Networks (CNNs) [3]-[4], leveraging Memristors on Edge of Chaos [5]-[6], fabricated at NaMLab [7]-[8], from a new perspective. The predictions, drawn from the theoretical investigation, shedding light on earlier-overlooked yet-critical subtleties behind these
emergent phenomena, are validated against the outcome of numerical investigations, for various
resistively-coupled Cellular Neural Networks, differing one from the other for the circuit topology of
the basic reaction cell. Given that neurons couple together in well-defined clusters for specific time
windows, depending upon the computational problem, they aim to solve, thus implementing sparse
spatio-temporal paradigms to code and process information in an energy-efficient form, studying the bifurcation phenomena [9], leading to the steady-state formation of static [10] or dynamic patterns [11], which may possibly emerge across bio-mimetic cellular arrays, depending upon the clusters of reaction cells, which adaptive synaptic couplings let interact via diffusion processes, may inspire the design of innovative neuromorphic networks [12]-[15] mimicking bio-plausibly the operating principles of the human brain.

Acknowledgement: This research study was financially supported by the DFG in the framework of the project 528378584 “Under Voltage Control: Nb2O5 Based Locally Active Threshold Switches,” belonging to the CRC/TRR programme 528378584 “TRR 404 Next Generation Electronics with Active Devices in Three Dimensions (Active-3D)”.

Bibliography:
[1] C.H. Houpis, and S.N. Sheldon, “Linear Control System Analysis and Design with Matlab,” 6th edition, CRC Press, 729pp., 2013, ISBN-13: 978-1466504264 2013
[2] A. M. Turing, “The chemical basis of morphogenesis,” Philos. Trans. Royal Soc. London, B, Biol. Sci., vol. 237, pp. 37-72, Aug. 1952
[3] L.O. Chua, “CNNs: A Paradigm for Complexity,” World Scientific Publishing Co Pte Ltd, 332pp., 1998, ISBN13: 978-9810234836
[4] V. Ravichandran, Y. Huang, B. Flannery, T. Molom-Ochir, T. Maurer, S. Asapu, A. Abdel-Maksoud, N. Heermance, R. Yoo, J. Tackie, W. Zhao, Y. Ling, A. Guo, J.J. Yang, and Q. Xia, “Memristive cellular neural networks for fast in-pixel computing,” Nature Electronics, vol. 9, no. 2, pp. 189-199, 2026
[5] L.O. Chua, “Memristors on ‘edge of chaos’,” Nature Reviews Electrical Engineering, vol. 1, pp. 614-627, 2024
[6] S.J. Kim, T. Wang, R. Zhao, D. Rossetti, Y. Xu, J. Zhao, A. Ascoli, F. Corinto, R. Stanley Williams, and J.J. Yang, “Diffusive memristors in the edge of chaos,” Nature Communications, vol. 17, no. 7920, pp. 1-10, 2026, DOI: 10.1038/s41467-026-74640-6
[7] A. Ascoli, A.S. Demirkol, R. Tetzlaff, S. Slesazeck, T. Mikolajick, and L.O. Chua, “On Local Activity and Edge of Chaos in a NaMLab Memristor”, Frontiers in Neuroscience, vol. 15, no. 651452, 30pp., 2021, DOI: 10.3389/fnins.2021.651452
[8] https://www.namlab.com/
[9] A. Ascoli, A.S. Demirkol, N. Schmitt, R. Tetzlaff, and L.O. Chua, “Edge of Chaos Behind Bistability of the Inhomogeneous in Homogeneous Cellular Media,” Proc. of the IEEE Int. Conference on Metrology for Extended Reality, Artificial Intelligence and Neural Engineering (MetroXRAINE), Rome (Italy), 2022, DOI: 10.1109/MetroXRAINE54828.2022.9967680
[10] A. Ascoli, A.S. Demirkol, L.O. Chua, and R. Tetzlaff, “Edge of Chaos is Sine Qua Non for Turing Instability,”IEEE Trans. Circuits and Systems-I (TCAS-I): Regular Papers, vol. 69, no. 11, pp. 4596-4609, Nov. 2022, DOI: 10.1109/TCSI.2022.3194465
[11] A. Ascoli, A.S. Demirkol, L.O. Chua, and R. Tetzlaff, “Edge of Chaos Theory Resolves Smale Paradox,”IEEE Trans. Circuits and Systems-I (TCAS-I): Regular Papers, vol. 69, no. 3, pp. 1252-1265, 2022, DOI:10.1109/TCSI.2021.3133627
[12] Sung Mo Kang, D. Choi, J.K. Eshraghian, P. Zhou, J. Kim, B.S. Kong, X. Zhu, A.S. Demirkol, A. Ascoli, R. Tetzlaff, W.D. Lu, and L.O. Chua, “How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal Signal Generation,” IEEE Trans. Circuits and Systems-I (TCAS-I): Regular Papers, vol. 68, no. 12, pp. 4837-4850, 2021, DOI: 10.1109/TCSI.2021.3126555
[13] W. Yi, K.K. Tsang, S.K. Lam, X. Bai, J.A. Crowell, and E.A. Flores, “Biological plausibility and stochasticity in scalable VO2 active memristor neurons,” Nature Communications, vol. 9, no. 4661, 10pp., 2018, DOI: 10.1038/s41467-018-07052-w
[14] M.D. Pickett, and R.S. Williams, “Phase transitions enable computational universality in neuristor-based cellular automata,” Nanotechnology, vol. 24, no. 38, 384002(7pp.), 2013, DOI: 10.1088/0957-4484/24/38/384002
[15] S. Kumar, R.S Williams, and Z. Wang, “Third-order nanocircuit elements for neuromorphic engineering,” vol. 585, no. 7826, pp. 518-523, Nature, 2020, DOI: 10.1038/s41586-020-2735-

Bio:

A. Ascoli achieved a First Class Honors Master of Science Degree in Electronic Engineering at Universita’ degli Studi Roma Tre in 2001, and a Ph.D. degree in Electronic Engineering at University College Dublin in 2006. He serves the Department of Electronics and Telecommunications of Politecnico di Torino as Associate Professor since 2023. He was previously affiliated for 11 years with the Chair of Fundamentals of Electronics at Dresden University of Technology, where he was conferred the prestigious Habilitation title in Nonlinear Circuit Theory in 2022. He has a strong expertise in the modelling and investigation of nonlinear devices, circuits and systems. In particular, he has developed predictive physics-based compact models for memristor nanodevices from the non-volatile and volatile classes, discovered various peculiar phenomena, occurring in memristive physical media through ad-hoc theoretic investigations, and designed bio-inspired circuits and networks, extending the functionalities of state-of-the-art electrical systems. He is especially admired for pioneering theoretico-experimental studies, involving the design of reaction-diffusion cellular arrays, hosting locally-active threshold switches, for explaining longstanding open questions in science, including Turing’s instability problem and Smale’s paradox. He was a recipient of the Best Paper Award from the International Journal of Circuit Theory and Applications (IJCTA) in 2007, and of the Darlington Best Paper Award from IEEE Transactions on Circuits and Systems in 2023. He served IEEE CASS as Associate Editor for the Transactions on Circuits and Systems (TCAS-I) over the 2023-2025 three-year term, and as Senior Area Editor for the same Journal over the 2024-2025 two-year time frame. He has been the President of the IEEE Circuits and Systems Society (CASS) Technical Committee (TC) on Cellular Nanoscale Networks and Array Computing (CNNAC) from 2019 to 2021. He has been the President of the IEEE CASS TC on Cellular Nanoscale Networks and Memristor Array Computing (CNN-MAC) from 2021 to 2023. Prof. Ascoli is a member of the Chua Memristor Center (CMC) since its establishment in 2016.
He is involved in the newly-approved COST Action proposal European Network on NeuroMorphic
Computing (EuroNMC). As DFG Mercator Fellow for the project SFB/TRR404, involving scientists at NaMLab gGmbH, he is currently a Visiting Professor at the Chair of Nanoelectronics of Dresden
University of Technology hosted by Prof. Thomas Mikolajick

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Speaker: Prof. Boris Vaisband, University of California, , Irvine

Date: Wednesday, November 11, 2026

Time: 13:00 – 14:30 Israel Time

Language: English

Location: Room 506, Zisapel Building, Technion Haifa.

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Abstract:

The demand for computation and memory in applications such as large language models (LLM), has increased well beyond the reticle boundaries of a system-on-chip (SoC). Chiplet-based integration is a paradigm shift that shapes the way we design future high-performance systems. The concept is to step away from large SoCs that are limited by communication, thermal design power, and reticle size, toward a robust plug-and-play approach, where small, heterogeneous, off-the-shelf chiplets are seamlessly integrated on a single platform. The chiplets paradigm, together with advanced packaging technologies, supports designing ultra-large-scale hardware that is compatible with LLM-type applications. In this talk, we will discuss the current state-of-the-art and challenges in chiplet integration, introduce the silicon interconnect fabric (Si-IF)–a wafer-scale heterogeneous integration platform, and offer solutions to enable large-scale AI applications.

Bio:

Boris Vaisband (Senior Member, IEEE) is the Samueli Development Chair Assistant Professor at the University of California, Irvine, working on heterogeneous systems integration.

In 2024 he was a Visiting Professor at UCLA and the Acting Director of UCLA CHIPS, and from 2019 to 2024, an Assistant Professor at McGill University. He received a B.S. degree in Computer Engineering from the Technion – Israel Institute of Technology in 2011, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Rochester, in, respectively, 2012 and 2017. From 2017 to 2019, he was a Postdoctoral Scholar at UCLA. From 2008 to 2015, he held various hardware design positions at Intel, Cisco, and Google.

His current research interests are in chiplets-based systems, heterogeneous integration, advanced packaging, and neuromorphic systems, with a focus on circuits, EDA tools, and design methodologies for power delivery, communication, thermal aware design and floorplanning, and testing. Some applications of interest are ultra-large-scale artificial intelligence systems and high-performance computing.

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Speaker: Tuvia Liran

Date: Sunday, October 11, 2026

Time: 16:00 – 17:30 Israel Time

Location: Zoom

Language: English

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Abstract:

ULTRASAT is a space telescope that will monitor transient astronomical events, in NUV (220-280nm) wavelength. The mission was initiated and leaded by Weizmann Institute, and scheduled to be launched on 2028 to GEO orbit.

The technical requirements from the imager are unique and very demanding, forcing the need for custom design of the imager. The imager was fully developed in Israel – definition by Weizmann Institute, Design by Analog Value, while Tower delivered the IPs and manufactured the chips.

The presentation will address the following topics:

– ULTRASAT – mission overview

– Requirements from the imager

– Techniques used for dark current mitigation

– Advanced techniques used in design & process

– Architecture of the imager

– Mitigation of radiation effects

The chips are already processed and tested, and currently at integration stage. Since it is a scientific mission, the details are not confidential like most space projects.

Bio:

Tuvia Liran had >40 years of experience in VLSI development, including analog & digital design, process, testing, Q&R, packaging and more. He was a member of ULTRASAT management team and technical advisor, and edited a paper on the development of the imager. He was co-founder of Ramon.Space, where he was responsible, as CTO, for the development of the technologies for space applications. The components demonstrated extremely high immunity to all radiation effects, and company’s products had been selected for many space missions, including missions to Mars, Asteroids, Jupiter, Saturn, Sun, and many satellites.

He served as navigator in IAF during his military service.

The webinar is free but the registration is required. The Zoom link will be sent after registration.

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Speaker: Prof. Adam Teman, EnICS Labs, Bar-Ilan University

Date: 23 July,2026

Time: 11:30 Israel time

Language: English

Location: Room 506, Zisapel Building, Technion Haifa.

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Abstract:

On-chip memory dominates the area and power of nearly every modern chip, yet SRAM, its default solution, is costly: six transistors per bit, leaky, ratioed, and no longer scaling with logic. Conventional embedded DRAM is denser but needs special fabrication that keeps it out of standard processes. This talk makes the case for Gain-Cell embedded DRAM (GC-eDRAM), a fully logic-compatible dynamic memory that is smaller and lower-leakage than SRAM while retaining SRAM-like performance. Its central challenge is limited data retention, which will be surveyed across more than a decade of circuit, technology, and refresh techniques developed to tame it. The talk will then turn to recent directions: silicon-proven macros in advanced process technologies, GC-eDRAM as a substrate for in-memory and associative computing, cryogenic operation, and RAAAM Memory Technologies – the company that is commercializing the technology.

Bio:

Adam Teman is a Full Professor at the Faculty of Engineering at Bar-Ilan University and co-director of the Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Labs. His research spans low-power and energy-efficient integrated circuits, embedded memory, physical design, hardware for emerging computing paradigms, and educating the current and future generations of chip designers. He is also a co-founder of RAAAM Memory Technologies, which is commercializing high-density logic-compatible embedded memory.

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Registration closes on October 18th, 2026

Date: October 26, 2026

Time: 9:30 – 16:00 Israel Time

Location: Auditorium 1003, 10th floor, Meyer Building, Technion Haifa

Language: English

Bio:

Founder and CEO of DeepSpike, San Diego, California

Founder and Chairman of the Board of Brain Corp, San Diego, California

Founder and Editor-in-Chief of Scholarpedia – the peer-reviewed encyclopedia

Publications: https://scholar.google.com/citations?user=1JeBX-IAAAAJ

Abstract: 

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Speaker: Prof. Gabriel Rincon-Mora, Georgia Institute of Technology

Date: September 7, 2026, Monday

Time: 16:00 – 17:30 Israel Time

Location: Zoom

Language: English

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Abstract:

Switched-inductor power supplies are pervasive in electronics. This is because they deliver a large fraction of the power they draw from the input source with an output that is largely independent of the load. Keeping the output steady this way is ultimately the responsibility of the feedback controller. This talk uses insight and intuition to show how hysteretic, timed, and clocked peak/valley loops control their outputs and respond to sudden changes. The presentation also describes when sub-harmonic oscillations surface and how slope compensation suppresses them. It then shows how summing comparators work and how they can contract, offset, and compensate these control loops and how comparators limit their input-to-output translations in continuous conduction and output current in discontinuous conduction. With this background and understanding in hand, designing compact feedback controllers for switched-inductor IoT power supplies is not only possible but also more straightforward.

Bio:

Gabriel Alfonso Rincón-Mora is Motorola Solutions Foundation Professor, Fellow of the National Academy of Inventors (NAI), Fellow of the American Association for the Advancement of Science (AAAS), Fellow of the Institution of Engineering and Technology (IET), and Fellow of the Institute of Electrical and Electronics Engineering (IEEE). He’s received the IEEE Charles A. Desoer Technical Achievement Award, Distinguished Faculty Achievement Award, Charles E. Perry Visionary Award, Three-Year Patent Award, National Hispanic in Technology Award, IEEE Joseph M. Biedenbach Outstanding Engineering Educator Award, IEEE Outstanding Educator Award, Orgullo Hispano Award, Hispanic Heritage Award, State of California Commendation Certificate, and IEEE Service Award. His body of work includes 12 books, 8 handbooks, 4 book chapters, 44 patents, over 200 articles, over 26 commercial power-chip products released to production, 25 educational videos, and over 180 keynote addresses, distinguished lectures, and research seminars. URL: rincon-mora.gatech.edu.

The webinar is free but the registration is required. The Zoom link will be sent after registration.

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