Instructor:	Gil Bloch, NVIDIA Israel
Teaching Assistant:	TBD
Lectures:	13 hours, 3 days
Academic Points:	1pts
Exam:	May 21, 2024 – 1.5 hours (only for students registered for the exam)
Course Fees:	1700$ (See membership options)

For registration click here

Registration closes on April 14th 2024

May 19 – 21, 2024

Course Content:

Artificial Intelligence, and specifically deep neural networks become the single most interesting application. It is expected that a growing percentage of the world’s compute power will be dedicated to training and inferencing of neural networks for many tasks.

Training large neural network models such as Large Language Models (LLM) require specialized systems and standard datacenters cannot train such models in an efficient way.

This course aim to cover multiple aspects of designing and building high-performance large-scale datacenters (supercomputers) for modern and future neural network training. In this course, we will cover accelerated computing and the role of GPUs and specialized CPUs in future AI systems as well as the importance of high-performance interconnect.

The course consists of a series of lectures. Several lectures are based on published papers and other cover recent research performed in NVIDIA.

This course aims at several categories of participants. Novice participants can learn about design tradeoffs and directions. Moreover, participants with high performance networking experience can update their knowledge and will be able to tune their experience to the state-of-the art.

Topics:

This course will cover advanced topic in supercomputer system architecture focusing on the interconnection between the compute engines, including interconnect hierarchies, communication algorithms and in-network computing.

Prerequisites:

Computer Architecture (046267 or 236267) and Networks and Internet (044334)

Schedule:

Day 1 (19/05/2024)

1.1. Introduction to supercomputing systems – 9:30-10:45

Coffee break – 10:45-11:15

1.2. Convergence of HPC and Cloud – 11:15-12:30

Lunch break – 12:30-13:30

1.3. Distributed AI training techniques – 13:30-14:45

Coffee break – 14:45-15:15

1.4. Distributed AI training techniques – 15:15-16:30

Day 2 (20/05/2024)

2.1. Challenges in modern distributed AI training (data reduction) – 9:30-10:45

Coffee break – 10:45-11:15

2.2. Challenges in modern distributed AI training (data reduction/all-to-all) – 11:15-12:30

Lunch break – 12:30-13:30

2.3. In-network computing (data reduction) – 13:30-14:45

Coffee break – 14:45-15:15

2.4. In-network computing (programmability) – 15:15-16:30

Day 3 (21/05/2024)

3.1. System topology considerations (NUMA, PCI, NVLink, Network) – 9:30-10:45

Coffee break – 10:45-11:15

3.2. Routing and congestion control – 11:15-12:30

Lunch break – 12:30-13:30

3.3. Fault tolerance – 13:30-14:45

Coffee break – 14:45-15:00

3.4. Final Exam (students Only)*– 15:00-16:30

*The final exam is only for students who have registered for the course through the faculty

Bio:

Gil Bloch is an HPC and AI specialist with broad experience in fast interconnect technologies for clusters, datacenters and cloud computing. His current responsibilities include co-design and in-network computing for HPC and machine learning. Gil is a teacher of Fast Networks and RDMA programming in the Hebrew University of Jerusalem (HUJI) and in Ben Gurion University of the Negev (BGU).

Before working on in-network computing, Gil had multiple engineering and architecture positions including network adapters and switches ASIC design and architecture, RDMA offload ASIC and open-source networking software for high performance computing. Gil is an author/co-author of multiple patents in the area of computer networks and network adapters. Gil holds a BSc degree in Electrical Engineering from the Technion, Israel Institute of Technology.

Please leave your details here

19/05/2024 – 21/05/2024

Registration closes on April 14th 2024

 

Frequency synthesizers are universally used in a wide range of applications including clocking, communications, instrumentation, and radar. The most common architecture is the fractional-N frequency synthesizer which uses a nonlinear finite state machine to produce the desired frequency. Both the finite state machine itself and interaction between its output and nonlinearities in the implementation can lead to unwanted spurious periodic output frequency components (spurs) and excess noise. Understanding of the origins of these effects has led to the invention of novel mitigation strategies.

This talk will explain the underlying issues, explain some recent innovations, and highlight open problems.

 

Michael Peter Kennedy received the B.E. degree in electronics from the National University of Ireland, Dublin, the M.S. and Ph.D. degrees from the University of California, Berkeley, and the D.Eng. degree from the National University of Ireland. He has published and lectured on a range of topics in the field of nonlinear circuits and systems including oscillators, chaos, neural networks, mixed-signal testing, phase-locked loops, delta-sigma modulation and frequency synthesis. He was made an IEEE Fellow in 1998 for his contributions to the study of Neural Networks and Nonlinear Dynamics. He was awarded the IEEE Third Millennium Medal, the IEEE Circuits and Systems Society Golden Jubilee Medal, and the RIA Parsons Medal. He has held faculty positions at University College Cork, where he also served as Vice-President for Research and Innovation, and University College Dublin, where he is currently Professor of Microelectronic Engineering. He has had visiting appointments at BME, EPFL, Imperial College London, and the University of Pavia. He has provided consulting services to a number of semiconductor companies and was founding Director of Ireland’s Microelectronics Industry Design Association and the Microelectronic Circuits Centre Ireland. He served as President of the Royal Irish Academy from 2017 to 2020.

Important: participation is free of charge, but registration is required

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As reported in the report recently issued by the United Nations (Intergovernmental Panel on Climate Change – IPCC Report 2021), the benefits that technology provides to a green and sustainable economy are highly appreciated and under intense research and development globally. Circuits and Systems (CAS), which are the base for any system, can bring the needed functionalities and performances for reaching eco-friendly, circular, and practical solutions.

The IoT active connection in agriculture (as an example in Europe) are exponentially increasing, proving that Precision Agriculture is a very fast-growing research field, where more controlled quality production, water use optimization, and a lower spreading of pesticides and fertilizers are some key issues, serving the improvement of food quality, but also helping the respect of agriculture for the environment.

For reaching these targets, electronics are the perfect tool for interfacing the data sources, extracting the data and processing them, and obtaining the needed information along the whole food chain: from the farmer, and the professional stakeholders to the consumers.

In the Distinguished Lecture, an overview of electronics for precision agriculture will be presented, analyzing the possible solutions that can bring important innovations, advancing the actual strategies based on remote or indirect measurements, instead in-place measuring the plant and soil parameters (a.k.a. Let the Plants do The Talking), associated with more standard information derived from environmental conditions.

Application scenarios for crop monitoring, water control, information communication, and decision support will be presented. In particular, will be analyzed technologies for reaching the needed levels of low power and low cost, and the efficient ones to be applied to Agri-Food at the global scale, supporting also food security and sustainability.

 

Danilo Demarchi Full Professor at Politecnico di Torino, Department of Electronics and Telecommunications.

Micro&Nano Electronics, Smart System Integration, and IoTs for the Agri-Food Value Chain and for BioMedical Devices.

Visiting Professor at EPFL Lausanne (2019) and at Tel Aviv University (2018-2021).

Visiting Scientist (2018) at MIT and Harvard Medical School for the project SISTER (Smart electronic IoT SysTEms for Rehabilitation Sciences).

Author and co-author of 5 patents and more than 300 scientific publications in international journals and peer-reviewed conference proceedings.

Leading the MiNES (Micro&Nano Electronic Systems – http://mines.polito.it) Laboratory of Politecnico di Torino and coordinating the Italian Institute of Technology Microelectronics group at Politecnico di Torino (IIT@DET).

Founder and Editor in Chief of the IEEE Transactions on AgriFood Electronics – TAFE (https://ieee-cas.org/publication/ieee-transactions-agrifood-electronics).

Founder and General-Co-Chair of the IEEE Conference on AgriFood Electronics – CAFE (https://2023.ieee-cafe.org).

Founder and Vice-Chair of the IEEE CAS Special Interest Group on AgriFood Electronics.

2023-2024 Distinguished Lecturer for the IEEE CAS Society with the Lecture “Let the Plants Do the Talking: Smart Agriculture by the messages received from Plants and Soil”.

Member of the IEEE Sensors Council and the BioCAS Technical Committee. Associate Editor of the IEEE Open Journal on Engineering in Medicine and Biology (OJ-EMB).

General Chair of IEEE BioCAS (Biomedical Circuits and Systems) Conference in 2017 in Torino and founder of IEEE FoodCAS Workshop (Circuits and Systems for the FoodChain).

TPC Co-Chair of IEEE ICECS 2019, IEEE BioCAS 2021 and IEEE BioCAS 2022 conferences. General Co-Chair of IEEE BioCAS 2023.

Organizer of the 3^rd Seasonal School on AgriFood Electronics: Smart Technologies for a Sustainable Agriculture in Torino, September 2022.

 

Important: participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

 

 

Instructor:	Mingoo Seok, Columbia University
Lectures:	3 days
Course Fee:	1700$ (See membership options)

*Registration is open until June 15, 2023

Schedule

Day 1 (19/6/23):

1. SRAM-based in-memory computing (IMC) hardware
   1. Analog
   2. Digital
   3. IMC-based accelerator architecture

Day 2 (20/6/23):

1. Analog mixed-signal computing
   1. Charge-based correlation calculation for GPS
   2. Analog signal processing for speech recognition
2. Spike-based computing
3. Spike neural network accelerator
4. Divisive energy normalization in the spike domain

Day 3 (21/6/23):

1. Digital LDO
2. Metrics
3. Recent techniques
4. FoM and benchmark
5. In-situ error detection and correction (EDAC)
6. EDAC for setup timing error
7. EDAC for metastability

Please leave your details

*Registration is open until June 15, 2023

 

Shlomo Raikin completed his M.Sc in The Netherlands.

He returned to Israel and served as a CPU architect at Intel for 10 years.

He then spent 2 years in Mellanox and joined Habana when it started as the CTO, a role he holds till today.

For registration 

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

In this talk a few TIA design examples will be presented, covering different types of applications.

TIAs can be broadly grouped into two categories, i.e. closed-loop and open-loop topologies.

Closed loop TIAs generally have better frequency response precision and can achieve higher dynamic range, but typically have higher power dissipation and limited bandwidth.

Open loop topologies are preferred when very wide bandwidth or ultra-low power dissipations are required.

In wireless sensor networks or Internet-of-Things (IoT), bandwidth is limited but power dissipation is reduced to a minimum, leading to ultra-low-power TIAs that consume only a few uW.

In 5G FR1 receivers, TIAs with tens of MHz bandwidth and a very high dynamic range are required. Closed-loop architectures are dominant, often with complex op-amp architecture and with power consumptions in the order of a few mW.

In 5G FR2 receivers, TIAs with hundreds of MHz to a few GHz bandwidth are used, mostly based on open-loop topologies with power dissipations of tens of mW.

 

Danilo Manstretta Member, IEEE) received the Laurea degree (summa cum laude) and the Ph.D. degree in electrical engineering and computer science from the University of Pavia in 1998 and 2002, respectively.

From 2001 to 2003 he was with Agere Systems as a Member of the Technical Staff, working on WLAN transceivers and linear power amplifiers for base stations. From 2003 to 2005 he was with Broadcom Corporation, Irvine, CA, working on RF tuners for TV applications. In 2005 he joined the University of Pavia, where he is now an Associate Professor. His research interests are in the field of analog, RF, optical, and millimeter-wave integrated circuit design.

Dr. Manstretta has been a member of the Steering Committee of the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium since 2017. He was a TPC member for the same conference from 2006 to 2021. He became TPC co-Chair in 2022 and is the RFIC TPC chair in 2023. He was Guest Editor of the IEEE Journal of Solid-State Circuits May 2017 Special Section dedicated to the 2016 RFIC Symposium and Guest Editor of the IEEE Transactions on Microwave Theory and Techniques June 2018 Mini Special Issue dedicated to the 2017 RFIC Symposium. He is a member of the European Solid-State Circuit Conference (ESSCIRC) TPC since 2022. He is a Distinguished Lecturer of the Solid-State Circuits Society. He was co-recipient of the 2003 IEEE Journal of Solid-State Circuits Best Paper Award.

 

Important: participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website 

 

The ability to detect single photons with high sensitivity and precision is revolutionizing the image sensors field. Single-photon avalanche diodes (SPAD) not only are extremely sensitive, but they also retain with high accuracy the photon arrival time, which opens a whole new world of opportunities. Conventional image sensors circuitry is not anymore enough to manage this device, which requires a completely different readout chain.

In this lecture, an overview of the SPAD potential, with pros and cons, will be addressed. Typical circuit topologies employed in SPAD-based image sensors will be described, along with some examples of applications and current trends.

 

Matteo Perenzoni (M’09, SM’19) graduated in electronics engineering from the University of Padua, Italy, and received tPh.D. in Physics from the University of Ferrara, Italy.

In 2002, he collaborated with the University of Padua on mixed-signal integrated circuit design for channel decoding. In 2004, he joined the Fondazione Bruno Kessler (FBK), Trento, Italy, as a Researcher working at the Integrated Radiation and Image Sensors (IRIS) Research Unit. Meanwhile, he also taught courses on electronics and sensors at the Master and Doctorate School, University of Trento, Trento. In 2014, he was a Visiting Research Scientist with the THz Sensing Group, Microelectronics Department, TU Delft, The Netherlands. From 2017 to 2021 he led the IRIS Research Unit at FBK, working in the field of radiation and image sensors using custom and CMOS technologies. Since 2021 he is with the Sony Europe Technology Development Centre in Trento, Italy, leading the analog IC design team. His research interests include advanced CMOS image sensors with a focus on single-photon detection, THz image sensors, and optimization of analog integrated circuits.

Dr. Perenzoni has been a member of the Technical Program Committee of the European Solid-State Circuit Conference (ESSCIRC), from 2015 to 2021 and of the International Solid-State Circuit Conference (ISSCC) from 2018 to 2022.

 

Important: participation is free of charge, but registration is required

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website