Date: March 18, 2026 – Wednesday
Time: 17:00 – 18:30 Israel Time
Lecturer: Prof. Bibhu Datta Sahoo, University at Buffalo
Language: English
Abstract:
The rapid advancements in computing, communication, and networking technologies facilitated by the feature size scaling of transistors, have not only made connected devices, i.e., Internet-of-Things (IoT), possible but also resulted in volumes of data being generated by these devices, which has led to rapid advancements in the area of big-data analytics thereby ushering in a new era of artificial intelligence and machine learning hardware to make smart connected devices. We have reached an inflection point in the design of such smart connected devices: the machine learning hardware designer must look beyond conventional digital computing blocks and possibly revive analog computing. This has led to a new generation of analog designers who are combining conventional analog circuits with approximate computing techniques using conventional CMOS as well as emerging-devices compatible with CMOS to build energy-efficient systems. This talk begins with an overview of various Neural Network Architectures and the computing blocks needed to realize them. FPGA-based Convolutional Neural Network (CNN) architectures for energy-efficient inference engines for image/depth-image classification, and seizure prediction which also reduces the sensor-interface front-end power and the energy-per-bit needed to transmit the sensor information to the inference engine will be discussed next. Hardware techniques for memory augmented neural network (MANN) using novel magneto-electric FETs (MeFET) will be discussed as well. Various analog dot-product computation methodologies, viz., conductance-based, charge-based, and gm-based will be discussed next. An oscillator-based mixed-signal Spiking Neural Network (SNN) architecture and techniques to facilitate energy-efficient training-on-the-edge will be presented.
Biography:
Bibhu Datta Sahoo joined the faculty of the UB Department of Electrical Engineering as Professor in Fall 2023. He received the B.Tech. degree in Electrical Engineering from the Indian Institute of Technology (IIT), Kharagpur, India, in 1998, the M.S.E.E. degree from the University of Minnesota, Minneapolis, MN, USA, in 2000, and the Ph.D. E.E. Degree from the University of California, Los Angeles in 2009. From 2000 to 2006, he was with DSP Microelectronics Group, Broadcom Corporation, Irvine, CA, where he designed analog and digital integrated circuits for signal-processing applications. From December 2008 to February 2010, he was with Maxlinear Inc., Carlsbad, CA, where he was involved in designing RF Integrated Circuits for CMOS TV tuners. He has been a faculty at IIT Kharagpur, India for 6 years and Amrita University, India for 5 years. His research interests include mixed signal circuit design, analog computing, and machine learning hardware. He received the 2008 Analog Devices Outstanding Student Designer Award and was the co-recipient of the 2013 CICC Best Paper Award. He was the Associate Editor of IEEE Transactions on Circuits and Systems-II from Aug. 2014 to Dec. 2015. Since Aug. 2019 he has been the Associate Editor of IEEE Open Journal of Circuits and Systems. He is one of the IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2025-2026.
The webinar is free but registration is required.