Date: September 30, 2024
Time: 16:00 – 17:30 Israel Time
Abstract
Cryptographic cores such as Advanced Encryption Standard (AES) protect sensitive data algorithmically but are vulnerable to attacks using side-channel information. Malicious attackers can analyze a crypto-core’s power consumption and EM emission (called side channel leakage) while encrypting and revealing the sensitive key of the crypto-core non-invasively and at a low cost. Several approaches have been explored to improve security robustness against these side-channel attacks (SCA). Power management-based techniques are promising as they directly alter the current and EM signatures to weaken the correlations between the compute activity and current/EM signatures.
In this seminar, I shall provide an overview of the recent power management techniques for SCA resilience. I shall present our ongoing work on power management-based techniques such as (i) Galvanic isolation, which separates the encryption current loop from the external VCC/VSS pins, ultimately providing orders of magnitude SCA improvement, (ii) Power delivery approaches against fine-grain EM SCAs (iii) Voltage stacking utilizing single current loop for multiple compute activities thereby reducing the correlation between the current/EM loops and underlying compute activity. Finally, I will conclude the seminar by highlighting the SCA issues arising from adopting imminent power delivery technologies such as buried power rails and back-side power delivery in advanced CMOS technologies.
Bio
Jaydeep Kulkarni is an Associate Professor in the Chandra Department of Electrical and Computer Engineering and a Fellow of Silicon Labs Endowed Chair at the University of Texas at Austin. His current research is focused on machine learning hardware accelerators, in-memory computing, emerging nano-devices, heterogeneous and 3D integrated circuits, hardware security, and cryogenic computing. This research has been recognized with the NSF CAREER, SRC Innovator, Intel Rising Star, and Micron Foundation faculty awards. He has served as a Distinguished Lecturer for IEEE SSCS, CAS, and ED societies and as a TPC member for VLSI Symposium, CICC, ASSCC, DAC, ICCAD.
Important: the webinar is free of charge but registration is required
For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website