Deep neural network inference comes with significant computational complexity, making their execution until recently only feasible on power-hungry server or GPU platforms. The recent trend towards real-time embedded neural network processing on edge and extreme edge devices requires a thorough cross-layer optimization. The talk will analyze what impacts NN execution energy and latency. Subsequently, we will present different research lines of Prof. Verhelst’s lab exploiting and jointly optimizing NPU/TPU processor architectures, dataflow schedulers and conditional, quantized neural network models for minimum latency and maximum energy efficiency. This includes precision-scalable fully-digital designs, as well as compute-in-memory processors. Finally, this talk will make a case for more methodological design space exploration in the vast optimization space of embedded NN processors, using the ZigZag framework.
Marian Verhelst is a full professor at the MICAS laboratories of the EE Department of KU Leuven. Her research focuses on embedded machine learning, hardware accelerators, HW-algorithm co-design and low-power edge processing. Before that, she received a PhD from KU Leuven in 2008, was a visiting scholar at the BWRC of UC Berkeley in the summer of 2005, and worked as a research scientist at Intel Labs, Hillsboro OR from 2008 till 2011. Marian is a topic chair of the DATE and ISSCC executive committees, TPC member of VLSI and ESSCIRC and was the chair of tinyML2021 and TPC co-chair of AICAS2020. Marian is an IEEE SSCS Distinguished Lecturer, was a member of the Young Academy of Belgium, an associate editor for TVLSI, TCAS-II and JSSC and a member of the STEM advisory committee to the Flemish Government. Marian currently holds a prestigious ERC Starting Grant from the European Union, was the laureate of the Royal Academy of Belgium in 2016, and received the André Mischke YAE Prize for Science and Policy in 2021.
Important: The participation is free of charge, but registration is required
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