Supervisor: Prof. Eby Friedman
Place: Technion, EE building, Auditorium 1003 (10th floor)
Date: 24.2.11
Abstract:
You are kindly invited to a Workshop on :
3-dimensional integration of VLSI circuits – technical, challenges and opportunities
Thursday, 24 Feb 2011, 14:30-17:30
Auditorium Floor 10
| 14:15 – 14:30 | Registration & Light Refreshments |  |
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14:30 – 15:10 |
Recent Research in 3-D Circuit Design and Related Test Circuits Prof. Eby G. Friedman, University of Rochester, NY, USA |
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15:10 – 15:50 |
Variability Issues in 3-D Clock Distribution Networks Prof. Vasilis Pavlidis, EPFL, Switzerland |
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15:50 – 16:10 | Coffee Break | |
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16:10 – 16:50 | Design and Modeling Methodology of Vertical Interconnects (TSV, mC4…) for 3DI technologies in IBM Dr. David Goren, IBM, Israel |
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16:50 – 17:30 |
Cost Effectiveness of 3D Integration Options Prof. Dimitrios Velenis, IMEC, Belgium |