All-Digital Phase-Locked Loops (ADPLL)

047003 – All-Digital Phase-Locked Loops (ADPLL)

October  19,20,23  2022

Auditorium 1003, Mayer Bld.

Professor Robert Bogdan Staszweski, University College Dublin, Ireland  

 

Instructor: Prof. Robert Bogdan Staszweski
Teaching assistant: Itamar Melamed
Lectures: 13 hours, 3 days
Academic points: 1pts
Exam: TBD
Course Fee : 1700$ (see membership options)

For registration click here 

*Registration is open until August 18, 2022

 

Course Content:

The past two decades has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and highperformance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer
function precision, settling speed, frequency modulation capability, and amenability to integration with
digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also
exhibits advantages of better performance, lower power consumption, lower area and cost over the
traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced
by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional
phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for
detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an
analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits
are readily estimated and compensated using “free” but powerful digital logic.

Topics per Day:

Days 1 & 2: (7 academic hours) All-Digital Phase-Locked Loop (ADPLL)
Architecture and Implementation
This lecture presents a system-level view of the ADPLL.
1. Principles of phase-domain frequency synthesis
2. ADPLL closed-loop behavior
3. Direct frequency modulation of ADPLL
4. Alternative TX architectures using ADPLL and PA regulator
5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design

Day 3 Morning (3 academic hours): Digitally-controlled oscillator (DCO)
A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based
on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but
with a significant difference in one of the components: instead of continuously tuned varactor (variable
capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed
in either high or low capacitative state. The composite varactor performs digital-to-capacitance
conversion. This lecture presents a circuit and system level views of DCO.

Day 3 Afternoon (3 academic hours): Time-to-digital converter (TDC)
A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital
variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase
is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay
(about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level
implementation issues.

Prerequisites:

  • 044137 Electronic Circuits
  • 044202 Random Signals

Grading:

Written exam – 100%

Recommended Literature and Study Materials:

Book: R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New
Jersey: John Wiley & Sons, Inc., Sept. 2006. ISBN: 978-0471772552.

Instructor’s Bio:

Robert Bogdan Staszewski received the BSc (summa cum laude), MSc and PhD degrees from the University
of Texas at Dallas in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel Network
Systems in Richardson, TX, USA, working on SONET cross-connect systems for fiber optics
communications. He joined Texas Instruments in Dallas, TX, USA, in 1995 where he was elected
Distinguished Member of Technical Staff (2% of the technical population). Between 1995 and 1999, he
was engaged in advanced CMOS read channel development for hard disk drives. In 1999 he co-started a
Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally intensive
approaches to traditional RF functions for integrated radios in deep-submicron CMOS. He served as a CTO
of the DRP group between 2007 and 2009. In 2009, he joined Delft University of Technology in the
Netherlands where he is currently a guest Full Professor. Since 2014, he has been a Full Professor with
University College Dublin in Ireland. He has authored and co-authored seven books, 11 book chapters,
160 journal and 220 conference publications, and holds 220 issued US patents. His research interests
include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers,
as well as quantum computers. He is an IEEE Fellow and recipient of IEEE Circuits and Systems Industrial Pioneer Award.

For registration click here

*Registration is open until August 18, 2022

 

 

Reliability of Semiconductor Devices

046003 – Reliability of Semiconductor Devices

September  18-20, 2022

Auditorium 1003, Mayer Bld.

Dr. Eitan Shauly, Tower Semiconductor  

 

Instructor: Dr. Eitan Shauly
Teaching assistant: Efrat Ordan
Lectures: 13 hours, 3 days
Academic points: 1pts
Exam: TBD
Course Fee : 1700$ (see membership options)

For registration click here 

*Registration is open until August 18, 2022

 

Sylabus:

Detailed overview of reliability failure mechanisms and modeling, from the foundry perspective. Covered Physical and Environmental FEOL and BEOL qualification, Automotive.

Topics:

1 Introduction to Reliability and time degradation

Quality and Reliability; The Reliability bathtub

Failure in time and the acceleration factors (Temp, Voltage, Currents stress)

MTTF (Mean-time-to-Failure), MTBF (Mean-time-between-Failure), FIT (Failure-in-time)

Materials and device degradation vs time – modeling, Competing degradation mechanisms,

Definition of quality and reliability; Yield vs Reliability; Reliability Scaling,

Physical failure mechanisms (Intro): HCI, NBTI, EM, SM, ESD,; Latchup, Soft error

2 EM=Electromigration

Introduction-BEOL reliability concerns; Electromigration–definition; Mass motion and flux modeling; Blech length; Void formation; Stress effects

EM testing and qualification;

Grain Size dependency, Alloys, Barrier metals and other process related performances improvement, N7 and N5 BEOL solutions

EM LT as function of Width and length

EM under AC vs DC conditions; EM scaling limitations

3 SM = Stress Migration in solid Materials

Stress migration, void formation and growth

Stress migration modeling w/ and w/o dielectric all—around

Physics of stress migration; Nucleation; Activation diffusion volume

Resistance change due to voids growth, stress gradients

SIV = Stress-Induced-Voids

SIV modeling;

Layout solution, double via solution; Stacked via sensitivity, effect of misalignment

BEOL dielectric cracking

SM and SIV qualification

4 HCI=Hot Carrier Injection

Carriers’ mobility; currents and voltages in MOSFET under operation: Vt, Id, Ib, Is, CLM, SCE, DIBL,

HCI – mechanism and modeling; DAHC (Drain Avalanche Hot carrier), CHE (Channel hot Electron), SHE (Substrate Hot Electron), others; Lucky Electron Model,

Interface charge generation,

HCI degradation under worse case conditions in planar MOSFETs and FinFETs,

HCI qualification – measurement, analysis and modeling

HCI under AC conditions,

Process solutions to reduce HCI: DDD, spacer with LDD implant, HALO/Pockets;

HCI scaling and integration

5 NBTI=Negative-Bias-Temperature-Instability,

Degradation Mechanism and modeling; Interface traps; The Reactive-Diffusion (R-D) degradation model, PBTI;

Stress time and degradation saturation; NBTI recovery; Dynamic NBTI

Qualification and modeling; NBTI Temperature dependency; NBTI Voltage exponential dependency; Voltage/Field acceleration factor

Process dependency; Boron Penetration, ; Oxynitridization, DPN; Fluorine passivation,

6 GOI=Gate Oxide Integrity,

GOX scaling, interfaces, Leakage; Tunneling, TAT, Qbd, Vbd,; Layout sensitivity;

Weibull distribution

Charge inside GOX, C-V;

Vbd; SBD, HBD,

TDDB – physical mechanisms, IBM modeling,

Process Enhancement GOI

Capacitors reliability, with Oxide-Nitride-Oxide, Nitride, Ta2O5; HKMG (Hf-based); TDDB of FinFETs,

TDDB – Qualification and Modeling

IMD-TDDB

7 PID=Plasma Induced Damage,

The mechanism of PID; Plasma non-uniformity, shading

Degradation of dielectric layers during PID

Antenna Ratio: traditional definition; Antenna rules, calculations and examples; Limitation of the traditional ratio; Cumulative plasma damage

PID dependency on integration flow; PID dependency on Gate oxide;

PID stress and measurement methods, PID structures

Protection: bridging, protective diode; Well charging, protection

8 Environmental qualification and the foundry responsibility

Foundry TQV for platform development; SRAM TEG: structure, scaling, operation, layout

Level-2 qualification – Environmental tests

·       Early Life Failure Rate (ELFR) – calculation

·       Burin-In for screening

·       Random failures, x-ray soft error,

·       High-temperature operating life (HTOL)

·       Biased temperature and humidity (THB, 85/85)

·       Temperature cycling (TMCL)

·       Autoclave

9 Qualification; The fabless/foundry reliability and qualification “relationship”,

The foundry TQV for qualification and WLR in HVM;

Reliability characterization; JEDEC JP001 (1, 2, 3)

Examples for foundry physical reliability qual plan and results

Additional qualification needs (PID, DRV, CA, Cp/Cpk)

10 Reliability for Automotive;

IoT, Automotive, connectivity. Examples for different Automotive applications

Different qualification requirements for Automotive;

Reliability for Automotive; Cumulative failure and life-time

The mission profile; AEC-Q100; ZEVI, Environmental qualification and Burn-In

Quality and Manufacturing for Automotive; Risk management; IATF16949; The Zero-defect program’ Process Control for Automotive’ Continuance Improvement plan’ 8D report, Failure Analysis capabilities

DfA – Design-for-Automotive; Devices, rules, Guidelines and DfM’ SPICE modeling – Aging’ IPs, ISO26262’ ASIL, Safety Function’ Trace and tractability

11 ESD=Electrostatics Discharge,

ESD and Triboelectric; The (cost) impact of ESD; The level of voltage build-up, examples for failures,

ESD Prevention and protection,

ESD Modeling; HBM; MM; CDM

ESD Protection; example

 

References:

  • Reliability and Failure of Electronic Materials and Devices, Milton Ohring, Academic Press (1998)
  • Reliability Wearout Mechanisms in Advanced CMOS Technology (IEEE Press Series on Microelectronic Systems, Alvin W. Strong et al., John Wiley (2009)
  • Up to date list of papers.

Expected Results:

Fulfilling course requirements student is expected to be able to:

  1. Understand the different reliability mechanisms in CMOS devices,
  2. Understand the dependencies between the process and the stress conditions in the field on the failure rate
  3. Fully characterize and analyze the reliability performance and figure of merits of different devices, by carful understanding the different mechanisms and the reliability characterization.
  4. Deep understanding of the way the semiconductor devices operates under stress (transistors, capacitors, resistors and more) thus how to optimize them to achieve the needed performance, with emphasize on reliability for automotive

Prerequisites:

  • 044231 Electron Devices 1 (MOS)

Assignments:

The course will consist of: lectures, self-practice exercises (35% of the grade), and a final exam (65% of the grade).

Course schedule:

18-Sep’22 1 09:00 ~ 09:50 Course Introduction,
Introduction to Reliability and time degradation, (TAF, CAF, VAF), modeling
2 10:00 ~ 10:50 Physical failure mechanisms: HCI, NBTI, EM, SM, GOI, ESD, others
3 11:00 ~ 12:00 Electromigration: definition; Mass motion and flux modeling; Blech length; Void formation; Stress effects
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Electromigration – testing and qualification;
6 14:00 ~ 15:15 Electromigration: Grain Size dependency, Alloys, Barrier metals and other process related performances improvement, N7 and N5 BEOL solutions
7 15:30 ~ 17:00 Electromigration: LT as function of Width and length, AC vs DC conditions; EM scaling limitations.
Stress Migration: Introduction
8 17:10 ~ 18:00 Stress Migration: void formation and growth; SIV modeling; Layout solution, double via solution; Stacked via sensitivity, effect of misalignment
19-Sep’22 1 09:00 ~ 09:50 Hot-Carrier-Injection: mechanism and modeling; DAHC (Drain Avalanche Hot carrier), CHE (Channel hot Electron), SHE (Substrate Hot Electron), others; Lucky Electron Model,
2 10:00 ~ 10:50 HCI: HCI degradation under worse case conditions in planar MOSFETs and FinFETs, qualification – measurement, analysis and modeling, Process solutions to reduce HCI: DDD, spacer with LDD implant, HALO/Pockets; Aging
3 11:00 ~ 12:00 Negative-Bias-Temperature-Instability: Degradation Mechanism and modeling; Interface traps; The Reactive-Diffusion (R-D) degradation model, PBTI;
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 NBTI: Stress time and degradation saturation; NBTI recovery; Dynamic NBTI; Qualification and modeling; Process dependency; Boron Penetration, ; Oxynitridization, DPN; Fluorine passivation,
6 14:00 ~ 15:15 Gate Oxide Integrity: GOX scaling, interfaces, Leakage; Tunneling, TAT, Qbd, Vbd,; Layout sensitivity;
7 15:30 ~ 17:00 GOI: Weibull distribution; Charge inside GOX, C-V; TDDB – physical mechanisms, IBM modeling,
8 17:10 ~ 18:00 GOI / Tirgol
20-Sep’22 1 09:00 ~ 09:50 GOI: Process Enhancement GOI; Oxide-Nitride-Oxide, Nitride, Ta2O5; HKMG (Hf-based);
2 10:00 ~ 10:50 GOI:  TDDB of FinFETs, TDDB – Qualification and Modeling, IMD-TDDB
3 11:00 ~ 12:00 Plasma Induced Damage: The mechanism of PID; Plasma non-uniformity, shading, Antenna Ratio: traditional definition; Antenna rules, calculations and examples; Limitation of the traditional ratio; Cumulative plasma damage; Protection: bridging, protective diode; Well charging, protection
4 12:00 ~ 13:00 Lunch Break
5 13:00 ~ 13:50 Technology qualification: TEG, TQV, ELFR, Burn-In, HTOL, THB, 85/85
6 14:00 ~ 15:15 Technology qualification: TMCL, JEDEC JP001
7 15:30 ~ 17:00 Automotive: Reliability, AEC-Q100, ZEVI, Mission Profile, Quality, IARF16949, DFA, IPs, ISO 26262
8 17:10 ~ 18:00 Electrostatics Discharge: Mechanism, examples for failures, Prevention and protection, HBM, MM, CDM

 

Lecturer Bio:

Dr. Eitan N. Shauly received the B.Sc. degree in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, in 1989, and M.Sc. and Ph.D. degrees in materials engineering from the Technicon — Institute of Technology, Haifa, in 1995 and 2001, respectively. He has worked for Tower Semiconductor since 1989. During 1989–1994 he was a diffusion and ion implantation engineer. During 1994–1997 he was a device/Integration engineer, focusing on process integration and process modeling. Since 1998 he is doing integration, focusing on platform development, design rules, Design-for-Manufacturing and Automotive. Dr. Shauly is also teaching at the faculty of Material Engineering, Technicon Haifa, courses related to VLSI technology: “VLSI processing” and “CMOS Devices and Integration”.

 

For registration click here 

*Registration is open until August 18, 2022

“CMOS Image Sensors – Device and Design Considerations “

047003 – CMOS Image Sensors – Device and Design Considerations

October 17-19, 2021

Room 1003, Mayer Bld. Electrical Engineering Dept. Technion

 Dr. Amos Fenigstein, Tower Semiconductors, Israel

Instructor:                    Dr. Amos Fenigstein

Teaching assistant:    Shlomi Bouscher

Lectures:                     13 hours, 3 days

Academic points:       1pts

Exam:                           28.10.21,  14.30-16:30  and/or  25.11.21, 14.30-16:30

 

Topics

The course will cover image sensors (IS) principles, building blocks, characterization and optimization, including IS optics, device physics, performance parameters and advanced schemes.

Prerequisites

  • (044231) Electron Devices 1 (MOS)
  • (046237) Introduction to VLSI
  • (044202) Stochastic Signals – recommended

Assignments

The course will consist of: lectures, self-practice exercises (25% of the grade), and a final exam (75% of the grade).

Course Abstract and Outline

This course deals with Image Sensors, starting with general requirements and specifications, sensor optics, image formation, resolution, Modulation Transfer Function (MTF), temporal and spatial noise, signal to noise ratio, and dynamic range. The course is focused on sensing devices, Charge Coupled Devices (CCD) and especially CMOS Image Sensors (CIS) where the modern CIS devices have CCDs-like components.  The course especially emphasizes the Silicon device underlying the pixels. The course discusses in details the 3T and the 4T pixel technologies with buried, and with fully pinned (fully depleted) diodes.  Different schemes of noise cancellation, advanced global shutter mode pixels and different schemes for wide dynamic range imaging will be discussed. There will be a short discussion on depth sensor based on time-of-flight (ToF) and the way they are implemented with CIS technology.

Course schedule:

17.10.21:

9:30-10:45 – Image Sensor Introduction – history and applications

10:45-11:15 – Coffee break

11:15-12:30 – Image Sensor optics, from scene to image, and image irradiance

12:30-13:30 – Lunch break

13:30-14:45 – Image Sensor optics – Chief Ray Angle (CRA) and microlens                                   shift, Resolution and Modulation Transfer Function (MTF)

14:45-15:15 – Coffee break

15:15-16:30 – Semiconductor physics essentials, light absorption and its                                      optimization

18.10.21:

9:30-10:45 – Device physics essentials, CIS pixel components

10:45-11:15 – Coffee break

11:15-12:30 – Pixel basics, the 3T pixel and its noise sources, pixel characterization

12:30-13:30 – Lunch break

13:30-14:45 – The kTC noise, noise suppression and cancellation

14:45-15:15 – Coffee break

15:15-16:30 – Modern image sensors – The pinned photodiode and the 4T pixel

19.10.21:

9:30-10:45 – Charge transfer –CCD principle, the buried CCD

10:45-11:15 – Coffee break

11:15-12:30 – Rolling and global shutter operation modes, and the shutter                                    efficiency

12:30-13:30 – Lunch break

13:30-14:45 – High Dynamic Range Schemes

14:45-15:15 –  Coffee break

15:15-16:30 – ToF sensors, iToF and dToF

Lecturer Bio

Dr. Fenigstein has been serving as Senior Director of R&D for Image Sensors since 2005. During these past years, his team has developed a wide range of CIS pixel technologies, from high-end cameras and industrial fast global shutter sensors, to large X-ray sensor and SPAD devices. Dr. Fenigstein has been with Tower since 2001 starting as device engineering manager. Before joining Tower, he managed a failure analysis team at Intel for its flip chip technology in the years 1998 – 2001.  Prior to Intel, he worked for SCD on state-of-the-art MCT far infrared image sensors. Dr. Fenigstein received his B.Sc., M.Sc. and D.Sc. (Quantum Well IR sensors) in Electrical Engineering from the Technion – Israel Institute of Technology, where he currently lectures on CMOS and CIS technology.

Introduction to Digital Radio Frequency Circuit Design”

May 19-June 30, 2021, Zoom

Instructor:                    Dr. Ofir Degani and guest lecturers from Intel

Teaching assistant:   Itamar Melamed (itamar.m@campus.technion.ac.il )

Lectures:                       26 hours, 6 weeks.

Academic points:       2pts

Exam:                             final project

 

Topics

The course will cover the operation principles and the design of modern digital radio frequency circuit topologies and system architectures with enhanced digital signal processing.

Prerequisites

  • Linear Electronic Circuits (044142) or Electronic Circuits (044137)
  • Receiving and Transmitting Techniques (044214) or RFIC (046903)

Assignments

The course will consist of: lectures, discussion, practical examples, and a final project.

The grade will be based on quizzes (30%) and the final project (70%).

The individual projects will include a transistor level schematic design project of a selected circuit based on the course topics (e.g., TDC, DTC) according a required specifications. The project will be mentored by the course guest lecturers. The project options will be published during the course.

A 30 min presentation (followed by 10 min for questions) of the project is expected covering the project goals, design methodologies used, and simulation results. The grade will be set by a committee of the course staff and the guest lecturers reviewing the presentation.

Course Abstract and Outline

The increasing demand for over-the-air data traffic imposes requirements for wireless protocols and transceivers to support wider (e.g., 160 MHz) channel bandwidths, higher order modulation schemes (e.g., 1k-QAM OFDM), and MIMO and multilink schemes to allow for the increased wireless throughput. As many wireless enabled devices are battery powered and mobile, there is also a continuous demand to improve power consumption, cost, and form factor. Reducing the power dissipation becomes even more critical with the simultaneous operation of multiple chains.

These trends have driven higher levels of integration of the radio, with digital SoCs, on advanced CMOS processes. However, implementing the transceiver on a deeply scaled process node presents major challenges from having to operate off low supply voltages. In addition, traditional RF designs require accurate transistor and passive models, which can become a time-to-market limitation for the whole SoC.

As a result, in recent years, there has been a shift in wireless transceivers toward digital radio architectures due to their more compact die area, scalability in advanced CMOS processes, and the improved power efficiency. Furthermore, digital circuit topologies open paths to include digital processing algorithms that can enhance the circuit capabilities beyond the traditional analog designs allow. Examples for such topologies include digital phase lock loops and digital transmitters that will be explored.

The course discusses the operation principles and the design of modern digital radio frequency circuit topologies and system architectures with enhanced digital signal processing. Two main examples will be presented and discussed in detail, the first of digital phase lock loops and the second of digital transmitters. Their basic operation principles and modeling will be discussed and compared to the equivalent analog radio components.

Course schedule:

19.05.21 Dr. Ofir Degani – 17:00-19:00

Introduction to Digital Radio Frequency Transmit and Receive (RF-TRX) circuits. Comparison vs. Analog RF-TRX, motivations, examples from literature

24.05.21: Dr. Evgeny Shumaker – 17:00-19:00

Introduction to phase lock loops (PLL), basic structure and operation principles of Analog PLL and Digital PLL. DPLL model and jitter/phase noise budgets – Part 1

26.05.21: Dr. Evgeny Shumaker – 17:00-19:00

Introduction to phase lock loops (PLL), basic structure and operation principles of Analog PLL and Digital PLL. DPLL model and jitter/phase noise budgets – Part 2

31.05.21: Rotem Banin – 17:00-19:00

Introduction to Time to Digital Converters (TDC), resolution, noise and meta stability, flash TDC, Vernier TDC, interpolating TDC & stochastic TDC, Part 1

02.06.21: Rotem Banin – 17:00-18:00

Introduction to Time to Digital Converters (TDC), resolution, noise and meta stability, flash TDC, Vernier TDC, interpolating TDC & stochastic TDC, Part 2

07.06.21: Run Levinger – 17:00-19:00

Introduction to Digitally Controlled Oscillators, frequency resolution, noise modeling – Part 1

09.06.21: Run Levinger – 17:00-18:00

Introduction to Digitally Controlled Oscillators, frequency resolution, noise modeling – Part 2

14.06.21: Assaf Ben-Bassat – 17:00-19:00

Introduction to RF Transmitters (TX), basic structure and operation principles of Analog TX (ATX) and Digital TX (DTX). Types of digital transmitters and their working principles: quadrature DTX, 2 point polar DTX, DTC based polar DTX

16.06.21: Elan Banin – 17:00-19:00

DTX signal generation Digital front end (DFE), non regular time sampling: FSRC, zero crossing algorithms

17.06.21: Shahar Gross – 17:00-19:00

Basic performance indicators for digital TX chains and impairments. Pre-distortion techniques

21.06.21: Dr. Gil Asa – 17:00-19:00

Introduction to digital to time converters (DTC) and operation principles. DTC architectures segmentation, coarse phase modulators (MUX based, multi modulus divider based), fine phase modulators (delay based, interpolation based). Non idealities and non linearities – Part 1

23.06.21: Dr. Gil Asa – 17:00-19:00

Introduction to digital to time converters (DTC) and operation principles. DTC architectures segmentation, coarse phase modulators (MUX based, multi modulus divider based), fine phase modulators (delay based, interpolation based). Non idealities and non linearities – Part 2

28.06.21: Dr. Ashoke Ravi – 17:00-19:00

Introduction to digital power amplifiers (DPA) and operation principles. Current mode RF DAC/DPA vs. capacitive mode RF DAC/DPA – Part 1

30.06.21: Dr. Ashoke Ravi – 17:00-19:00

Introduction to digital power amplifiers (DPA) and operation principles. Current mode RF DAC/DPA vs. capacitive mode RF DAC/DPA – Part 2

Lecturer Bio

Ofir Degani (Senior Member, IEEE) has received the B.Sc. degree (summa cum laude) in electrical engineering and the B.A. degree in physics (summa cum laude) and the M.Sc. and Ph.D. degrees all from the Technion—Israel Institute of Technology, Haifa, Israel, in 1996, 1999, and 2005, respectively. His Ph.D. research was on MEMS inertial sensors and electrostatic actuators.

He joined the Mobility Wireless Group, Intel Corporation, Haifa, in 2006. His recent research interest includes integrated transceivers, digital transmitters, and mmWave radios in CMOS technology. He has authored or coauthored more than 80 journal articles and conference papers. He has filed more than 50 patents.

Dr. Degani was a recipient of the prestigious 2002 Graduate Student Fellowship from the IEEE Electron Devices Society and the Charles Clore Scholarship at the Charles Clore Foundation.

Guest Lecturers Bios

Assaf Ben-Bassat (Member, IEEE) received the B.Sc. and M.Sc. degrees in electrical engineering from the Technion—Israel Institute of Technology, Haifa, Israel, in 1997 and 2001, respectively, with a focus on the field of electro-optics.

From 2001 to 2003, he was with All-Optical, Haifa, developing lasers for high-speed optical communications. He joined Intel Corporation, Haifa, in 2003, where he develops circuits for baseband, RF, PLLs, and LO generation and distribution.

Shahar Gross received the B.Sc. degree in physics and the B.Sc. and M.Sc. degrees in electrical engineering from Tel Aviv University, Tel Aviv, Israel, specializing in signal processing, communication, and information theory.

In 2012, he joined as a PHY System Engineer with the Wireless Products Division, Intel Corporation, Petach-Tikva, Israel, where he is currently a PHY architect and is focused on advanced transmitter features. He took part in the Wi-Fi 6 standardization process and led the Wi-Fi PHY architecture of Intel’s first Wi-Fi 6 product.

Elan Banin received the B.Sc. degree in mechanical engineering from Tel Aviv University, Tel Aviv, Israel, in 2006.

He joined Intel Corporation, Petach-Tikva, Israel, in 2010, where he has worked as a DSP and Algorithms Engineer on multiple communication technologies.

Rotem Banin received the B.Sc. degree in electrical engineering from the Technion—Israel Institute of Technology, Haifa, Israel, in 2006, and the M.Sc. degree from Tel Aviv University, in 2015, Israel.

He joined the Mobility Wireless Group, Intel Corporation, Haifa in 2003. His recent research interest includes high-speed mixed-signal circuits and systems, integrated transceivers, digital transmitters, digital PLLs, and serial interfaces.

Ashoke Ravi (Senior Member, IEEE) received the B.Tech. degree in electrical engineering from IIT Madras, Chennai, India, and the M.S. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA.

In 2001, he joined Intel Corporation, Hillsboro, OR, USA, where he is currently a Principal Engineer, working on innovation projects with the Advanced Radio Technology Team. His prior contributions were in developing integrated RF transceivers on deeply scaled CMOS processes and MIMO radios. He has authored or coauthored 50 IEEE conference papers and journal articles and coauthored three book chapters. He has 35 issued patents in this field. His research interests are in RF and mixed-signal circuits and architectures for connectivity, cellular, and SoC applications. Over the last several years, these activities have included leading the research and development of mm-waveband transceivers, digital polar and outphasing transmitters, digital PLLs, and data converters.

Dr. Ravi was nominated to the MIT Technology Review’s list of top 35 young innovators (the TR35) in 2009.

Gil Asa (Ph.D.) has received B.Sc. , M.Sc. , Ph.D. (all summa cum laude, from the Technion -IIT), focusing on micro-electronics. He graduated Ph.D. at 1999 researching advanced nuclear camera and detectors. At 1998 he took part in the Technion Israeli satellite project with design of Gamma ray spectrometer, which reports supernova activities. Till 2002 he was a project leader at IBM research labs working on ultra-high speed SiGe serializers, and till 2006 he was a senior circuit designer at Marvell working on self-invented digital PLL. Till 2012 he was the founder and CTO of compact SRAM start up and till 2015 he was an analog expert consultant at Inomize, working on video camera implanted inside the eye of partially blind patients. Since 2015 he joined Intel as signal integrity leader and since 2017 the focus is on RF circuit design, digital transmitters and relevant IP development. Dr. Asa has at least 10 academic papers, and over 25 worldwide patents (10 of them as sole inventor).

Run Levinger received the M.Sc. degree (Summa Cum Lauda) in electrical and electronics engineering from Tel-Aviv University, Tel Aviv, Israel, in 2015. His research thesis focused on linearization techniques for integrated E-band transmitter circuits such as up-converting mixers and power detectors. In 2011, he joined the IBM Haifa Research Laboratories, Haifa, Israel, where he was a Research Staff Member with the mm-Wave Technologies Group. In 2016, he joined Intel’s Radio Product Development group, Petah-Tikva, Israel, where he is a senior technical staff member. His research interests include designing, measuring, and modeling of integrated RF and millimeter-wave voltage and digital controlled oscillators (VCOs and DCOs), frequency synthesizers, frequency dividers, mixers, power detectors, and passives

for communication, radar, and imaging applications. He has Authored and Co-Authored more than 25 Conference and Journal papers and holds 10 US patents with several more pending.

Evgeny Shumaker graduated B.Sc. (summa cum laude), M.Sc. (summa cum laude) and Ph.D. degrees all from the Electrical Engineering department, Technion—Israel Institute of Technology, Haifa, Israel, in 2002, 2004, and 2010, respectively. His Ph.D. dissertation focused on basic limits and applications of slow and fast light phenomenon in microwave photonics.

In 2010 he joined IBM Haifa Research Laboratory where he was a Research Staff Member, leading R&D of passive millimeter wave imaging systems. In 2015 he joined Intel’s Radio Product Development group, Haifa, Israel, where he is currently a Senior Technical Staff Member. His research interests include real-time algorithms and techniques for high precision digital frequency synthesis. He has authored or coauthored more than 40 journal articles and conference papers and filed more than 10 patents.

Dr. Shumakher is a two-time recipient of the E.I. Jury award (2004, 2009) and the prestigious Graduate Student Fellowship from the IEEE Photonics Society (2009).

Highly-Integrated Millimeter-Wave Radar Systems in Silicon-Based Technologies

February 23-25, 2020

Instructor:                    Prof. Vadim Issakov, OVGU Magdeburg, Germany

Teaching assistant:   Nimrod Ginzber (nimrodg@campus.technion.ac.il)

Lectures:                       13 hours, three days.

Academic points:       1pts

Exam:  28/02/2020 at 9:00 and/or 20/03/2020 at 9:00

 

Topics

This course will cover advanced topics in radar systems from system calculation to mm-wave circuit design and integration with antennas.

 

Prerequisites

  • 044142 | Linear Electronic Circuits or
  • 044137 | Electronic Circuits

Assignments

The course will consist of: lectures, discussion, practical examples, exam.

Course Abstract and Outline

Recent advances of silicon-based semiconductor processes and packaging technologies have accelerated the implementation of radar sensors for numerous mass-volume applications at mm-wave frequencies. CMOS and SiGe technologies seem to provide a very attractive solution for realization of mm-wave radar transceivers.

This first part of the lecture will start with the basic introduction of continuous-wave (CW) and pulsed radar systems. We discuss briefly the frequency regulations for automotive and consumer radar applications. Then we focus only on CW and FMCW systems and consider range, velocity and angular resolution. We discuss how to derive a specification of the radar system based on the specific radar application scenario, as e.g. link budget calculation, frequency chirp, dimensioning of filters and VGA in the analog baseband, choosing sampling rate and resolution of the ADC. Next, we discuss the impact of phase noise on radar systems, as e.g. range correlation effect. Further, we discuss the radar signal processing, range-Doppler map and detection of multiple targets. Finally, we discuss advanced topics as noise floor degradation by non-ideal mixing and TX to RX spillover cancellation and show integrated radar system examples. Then, we derive specification of the circuit blocks based on the system requirements and adress the design of the blocks separately in the second part.

The second part deals with the circuit design and physical implementation of the systems on chip (SoC) and systems in Package (SiP) for mm-wave radar applications. First, we repeat the basics of mm-wave design, as e.g. CMOS and bipolar transistor performance at mm-wave, passives at mm-wave, nonlinearity, noise, stability. Next, we discuss the design of mm-wave LNA, mixers (active and passive), VCO, Power Amplifier, frequency divider and multiplier. We discuss considerations on LO synthesis and distribution for large chips. Additionally, we discuss realization challenages of antenna on-chip and in package at mm-wave frequencies. Finally, we discuss examples of latest reported radar transceivers.

This course aims to provide a deep overview over modern radar systems for automotive and consumer applications. The students will get a broad scope starting from the radar sensing scenario, translating it into the block specification, designing the circuit blocks and realization of the transceivers. Novice designers can get an introduction to circuits and systems, while experienced mm-wave designers can expand their knowledge by connecting the circuits and systems for radar applications.

Course schedule:

23.02.20:

09:30-10:45 – Introduction to Radar Systems and Radar Fundamentals

10:45-11:15 – Coffee break

11:15-12:30 – Doppler Radar and Pulse Radar

12:30-13:30 – Lunch break

13:30-14:45 – FMCW Radar and Chirp-Sequence Radar

14:45-15:15 – Coffee break

15:15-16:30 – Advanced Effects in FMCW Systems

 24.02.20:

09:30-10:45 – Systematic Design Steps of FMCW Radar Systems

10:45-11:15 – Coffee break

11:15-12:30 – Specification Calculation of RF Circuit Blocks & Analog Baseband

12:30-13:30 – Lunch break

13:30-14:45 – Fundamentals of mm-wave Circuit Design

14:45-15:15 – Coffee break

15:15-16:30 – LNA Design

 25.02.20:

09:30-10:45 – Mixer Design

10:45-11:15 – Coffee break

11:15-12:30 – Power Amplifier Design

12:30-13:30 – Lunch break

13:30-14:45 – LO Generation and Distribution

14:45-15:15 – Coffee break

15:15-16:30 – Antenna on-chip and in-package and State of the Art Systems

Lecturer Bio

Vadim Issakov received the M.Sc. degree in microwave engineering from the TU Munich in 2006 and the Ph.D. degree from the University of Paderborn, Germany, in 2010. He received an award for the outstanding dissertation from the VDE (German Association of Engineers) and best dissertation award from the University of Paderborn.

In March 2010 he joined Infineon in Neubiberg, Germany. Afterwards he worked at IMEC and Intel Corporation, before he came back to Infineon in August 2015 as mm-wave Design Lead and Principal Engineer leading a research group working on pre-development of mm-wave radar and communication products. His work has been recognized by the IEEE MTT Outstanding Young Engineer Award. Since 2014 he was teaching classes on Analog RF CMOS Circuits and Highly-integrated mm-wave Circuits as Adjunct Lecturer at the University of Bochum and University of Erlangen, Germany. In September 2019 he joined the University of Magdeburg, Germany, as a full professor holding the Chair for Electronics.

Nanoscale Design Methodologies for Low-Power and Robust Gigascale

Supervisor: Prof. Volkan Kursun

Place: Technion

Date: 22.6.08

Abstract:

CIRCUIT DESIGN TECHNIQUES FOR LOW-POWER AND ROBUST NANOSCALE INTEGRATION

DAY, 1 22 June 2008

9:30-11:00    Domino logic and body biasing

11:30-13:00  Multi-Threshold circuits (MTCMOS)

14:00-15:30  Memory circuits

16:00-17:30  Power supply switching and voltage conversion circuits

DAY 2, 23 June 2008

9:30-11:00  Design techniques for variation tolerant circuits

11:30-13:00 Temperature-adaptive circuits

14:00-15:30 Designing with FinFET transistors I

16:00 – 17:30  Designing with FinFET transistors II

Volkan Kursun

Assistant Professor

Biography

Volkan Kursun received the B.S. degree in Electrical and Electronics Engineering from the Middle East Technical University, Ankara, Turkey in 1999, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, New York in 2001 and 2004, respectively.

He performed research on mixed-signal thermal inkjet integrated circuits with Xerox Corporation, Webster, New York in 2000. During summers 2001 and 2002, he was with Intel Microprocessor Research Laboratories, Hillsboro, Oregon, responsible for the modeling and design of high frequency monolithic power supplies. He has been an assistant professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison  since 2004.

His current research interests are in the areas of low voltage, low power, and high performance integrated circuit design, modeling of semiconductor devices, and emerging integrated circuit technologies.

Dr. Kursun is an associate editor of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the IEEE Transactions on Circuits and Systems I, the IEEE Transactions on Circuits and Systems II, and the Journal of Circuits, Systems, and Computers (JCSC) and an organizing / technical program committee member of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), ACM/SIGDA Great Lakes Symposium on VLSI (GLSVLSI), IEEE International Symposium on Circuits and Systems (ISCAS), IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), and the IEEE/ACM International Symposium on Quality Electronic Design (ISQED).

 

Contact:

Phone: 608-262-8804

Fax: 608-262-8804

E-mail: kursun@engr.wisc

Mixed-Signal Circuit and Architecture Design for CMOS Data Converters

Supervisor: Prof. Murmann

Place: Technion

Date: 28-12-08

Abstract: 

Dates: 28-30 December 2008
Location: Meyer building, Department of electrical engineering, Technion, Haifa, Israel
This course will cover the design of mixed-signal integrated circuits for implementing the interfaces between analog and digital signals in CMOS VLSI systems. Topics include fundamental circuit elements such as comparators, track-and-hold circuits, and operational transconductance amplifiers. Architecture-specific material will focus on pipeline ADCs and current-steering DACs. The course ends with a discussion on technological limits and current research topics.
 
Sunday:
08:30-10:00, 10:30-12:00 Data converter architectures, specifications and trends; voltage comparator design
13:30-15:00, 15:30-17:00. Track-and-hold circuit design, analysis of nonidealities such as noise and distortion
Monday:
08:30-10:00, 10:30-12:00 Operational transconductance amplifiers, gm/ID based design
13:30-15:00, 15:30-17:00 Pipeline ADCs, architecture and circuit design
Tuesday
08:30-10:00, 10:30-12:00 Fundamentals of Nyquist DAC design; data converter testing
13:30-15:00, 15:30-17:00 Limits on ADC power dissipation; research topics
  
Prof. Boris Murmann, Stanford University
Short biography
Boris Murmann received the Dipl.-Ing. (FH) degree in communications engineering from Fachhochschule Dieburg, Germany, in 1994, and the M.S. degree in electrical engineering from Santa Clara University, Santa Clara, CA, in 1999. In 2003, he received the Ph.D. degree in electrical engineering from the University of California at Berkeley.
From 1994 to 1997, he was with Neutron Mikrolektronik GmbH, Hanau, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. During 2001 and 2002, he held summer positions with the High-Speed Converter Group at Analog Devices, Wilmington, MA. Since 2004, he has been an Assistant Professor in the Department of Electrical Engineering, Stanford, CA. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces.
At UC Berkeley, Dr. Murmann received the outstanding graduate student instructor award in 1999 and the CalView award for excellence in distance education in 2003. He was a co-recipient of the Meritorious Paper Award at the 2005 US Government Microcircuit & Critical Technology Conference. Dr. Murmann served as a guest editor for the EURASIP Journal on Advances in Signal Processing in 2007. He currently serves as a member of the International Solid-State-Circuits Conference (ISSCC) program committee.

Course Material

 

Low Power CMOS Circuit Design

Supervisor: Professor Yusuf Leblebici

Place: Auditorium Floor 10, Electrical Engineering Building, Technion

Date: 12-14 October 2009

Abstract: 

Seminar “Low Power CMOS Circuit Design”

12-14 October 2009

Professor Yusuf Leblebici

Yusuf Leblebici received the B.S. and M.S. degrees in electrical engineering from Istanbul Technical University in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990.

 

Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI), where he established and directed the VLSI Design Laboratory, and also served as a project director at the New England Center for Analog and Mixed-Signal IC Design. He also worked as the Microelectronics Program Coordinator at Sabanci University. Since January 2002, he has been a full professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of the Microelectronic Systems Laboratory. His research interests include design of high-speed and low-power CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, modeling and simulation of nano-electronic circuits, intelligent sensor interfaces, and VLSI reliability analysis. Dr. Leblebici is the coauthor of three textbooks, namely, “CMOS Digital Integrated Circuits: Analysis and Design” (McGraw Hill, 1996, 1999 and 2003), “Hot-Carrier Reliability of MOS VLSI Circuits” (Kluwer Academic, 1993), “CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications” (Springer, 2007) as well as more than 150 scientific articles published in international journals and conferences.

 

Dr. Leblebici has served on the organizing and technical program committees of the 1995 European Conference on Circuit Theory and Design (ECCTD 1995), the 2004 European Workshop on Microelectronics Education (EWME 2004), and as General Co-Chair of the Joint 2006 European Solid-State Circuits Conference and European Solid-State Device Research Conference (ESSCIRC-ESSDERC 2006). He also served as an Associate Editor of IEEE Transactions on Circuits and Systems II, and as an Associate Editor of IEEE Transactions on VLSI. He received the Young Scientist Award of the Turkish Scientific and Technological Research Councils in 1995, and the Joseph Samuel Satin Distinguished Fellow Award of the Worcester Polytechnic Institute in 1999.

 

Syllabus

Low Power CMOS Circuit Design

  1. Introduction to low power CMOS circuit design
    2. Dynamic (switching) and leakage power consumption
    3. Influence of technology scaling and nanometer CMOS
    4. Minimizing energy consumption under performance constraints
    5. Dynamic voltage-frequency scaling (DVFS) techniques
    6. Physics and modeling of subthreshold operation in MOSFETs
    7. CMOS logic operating in subthreshold regime
    8. Benefits and limitations of subthreshold operation in view
    of increased leakage in nanometer CMOS technologies
    9. Current mode operation for low power
    10. Subthreshold source-coupled logic (STSCL) circuits
    11. Complex logic gates using STSCL style
    12. Two-phase pipelining to improve activity rate
    13. Source-follower buffer drivers for large fanout
    14. Design automation for standard-cell based STSCL design
    15. Cell library creation, placement & routing techniques

 

Agenda

 

Monday 12.10.09

 

13:00 – 13:30 Registration

13:30 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 18:00 lecture

 

Tuesday 13.10.09

 

08:30 – 09:00 Coffee

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

 

Wednesday, 14.10.09

 

08:30 – 09:00 Coffee

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

 

Admission

Admission to the course is free of charge only to Members of the ACRC,

Brief RFIC seminar

Supervisor: Prof. Avinoam Kolodny

Place: Auditorium Floor 10, Electrical Engineering Building, Technion

Date: 25.1.10

Abstract:

Brief RFIC seminar

25.1.10

Floor 10, Room1007 Electrical Engineering Building, Technion

 

 

13:30 – 13:45 Reception & Light Refreshments

 

14:00 – 14:30 Dr. Christopher D. Hull

RF transceiver from 3.x towards 4G/ OFDM based systems

 

14:30 – 15:00 Dr. Ofir Degani

Past present and future CMOS Power amplifiers for Wireless

Communications

 

15:00 – 15:30 Coffee Break

 

15:30 – 16:00 Mr. Emanuel Cohen

60 GHz system and components in CMOS for low power compact

Phase Array applications Open discussion- 30 min

 

16:00 – 16:30 Discussion