Introduction to Digital Radio Frequency Circuit Design”

May 19-June 30, 2021, Zoom

Instructor:                    Dr. Ofir Degani and guest lecturers from Intel

Teaching assistant:   Itamar Melamed (itamar.m@campus.technion.ac.il )

Lectures:                       26 hours, 6 weeks.

Academic points:       2pts

Exam:                             final project

 

Topics

The course will cover the operation principles and the design of modern digital radio frequency circuit topologies and system architectures with enhanced digital signal processing.

Prerequisites

  • Linear Electronic Circuits (044142) or Electronic Circuits (044137)
  • Receiving and Transmitting Techniques (044214) or RFIC (046903)

Assignments

The course will consist of: lectures, discussion, practical examples, and a final project.

The grade will be based on quizzes (30%) and the final project (70%).

The individual projects will include a transistor level schematic design project of a selected circuit based on the course topics (e.g., TDC, DTC) according a required specifications. The project will be mentored by the course guest lecturers. The project options will be published during the course.

A 30 min presentation (followed by 10 min for questions) of the project is expected covering the project goals, design methodologies used, and simulation results. The grade will be set by a committee of the course staff and the guest lecturers reviewing the presentation.

Course Abstract and Outline

The increasing demand for over-the-air data traffic imposes requirements for wireless protocols and transceivers to support wider (e.g., 160 MHz) channel bandwidths, higher order modulation schemes (e.g., 1k-QAM OFDM), and MIMO and multilink schemes to allow for the increased wireless throughput. As many wireless enabled devices are battery powered and mobile, there is also a continuous demand to improve power consumption, cost, and form factor. Reducing the power dissipation becomes even more critical with the simultaneous operation of multiple chains.

These trends have driven higher levels of integration of the radio, with digital SoCs, on advanced CMOS processes. However, implementing the transceiver on a deeply scaled process node presents major challenges from having to operate off low supply voltages. In addition, traditional RF designs require accurate transistor and passive models, which can become a time-to-market limitation for the whole SoC.

As a result, in recent years, there has been a shift in wireless transceivers toward digital radio architectures due to their more compact die area, scalability in advanced CMOS processes, and the improved power efficiency. Furthermore, digital circuit topologies open paths to include digital processing algorithms that can enhance the circuit capabilities beyond the traditional analog designs allow. Examples for such topologies include digital phase lock loops and digital transmitters that will be explored.

The course discusses the operation principles and the design of modern digital radio frequency circuit topologies and system architectures with enhanced digital signal processing. Two main examples will be presented and discussed in detail, the first of digital phase lock loops and the second of digital transmitters. Their basic operation principles and modeling will be discussed and compared to the equivalent analog radio components.

Course schedule:

19.05.21 Dr. Ofir Degani – 17:00-19:00

Introduction to Digital Radio Frequency Transmit and Receive (RF-TRX) circuits. Comparison vs. Analog RF-TRX, motivations, examples from literature

24.05.21: Dr. Evgeny Shumaker – 17:00-19:00

Introduction to phase lock loops (PLL), basic structure and operation principles of Analog PLL and Digital PLL. DPLL model and jitter/phase noise budgets – Part 1

26.05.21: Dr. Evgeny Shumaker – 17:00-19:00

Introduction to phase lock loops (PLL), basic structure and operation principles of Analog PLL and Digital PLL. DPLL model and jitter/phase noise budgets – Part 2

31.05.21: Rotem Banin – 17:00-19:00

Introduction to Time to Digital Converters (TDC), resolution, noise and meta stability, flash TDC, Vernier TDC, interpolating TDC & stochastic TDC, Part 1

02.06.21: Rotem Banin – 17:00-18:00

Introduction to Time to Digital Converters (TDC), resolution, noise and meta stability, flash TDC, Vernier TDC, interpolating TDC & stochastic TDC, Part 2

07.06.21: Run Levinger – 17:00-19:00

Introduction to Digitally Controlled Oscillators, frequency resolution, noise modeling – Part 1

09.06.21: Run Levinger – 17:00-18:00

Introduction to Digitally Controlled Oscillators, frequency resolution, noise modeling – Part 2

14.06.21: Assaf Ben-Bassat – 17:00-19:00

Introduction to RF Transmitters (TX), basic structure and operation principles of Analog TX (ATX) and Digital TX (DTX). Types of digital transmitters and their working principles: quadrature DTX, 2 point polar DTX, DTC based polar DTX

16.06.21: Elan Banin – 17:00-19:00

DTX signal generation Digital front end (DFE), non regular time sampling: FSRC, zero crossing algorithms

17.06.21: Shahar Gross – 17:00-19:00

Basic performance indicators for digital TX chains and impairments. Pre-distortion techniques

21.06.21: Dr. Gil Asa – 17:00-19:00

Introduction to digital to time converters (DTC) and operation principles. DTC architectures segmentation, coarse phase modulators (MUX based, multi modulus divider based), fine phase modulators (delay based, interpolation based). Non idealities and non linearities – Part 1

23.06.21: Dr. Gil Asa – 17:00-19:00

Introduction to digital to time converters (DTC) and operation principles. DTC architectures segmentation, coarse phase modulators (MUX based, multi modulus divider based), fine phase modulators (delay based, interpolation based). Non idealities and non linearities – Part 2

28.06.21: Dr. Ashoke Ravi – 17:00-19:00

Introduction to digital power amplifiers (DPA) and operation principles. Current mode RF DAC/DPA vs. capacitive mode RF DAC/DPA – Part 1

30.06.21: Dr. Ashoke Ravi – 17:00-19:00

Introduction to digital power amplifiers (DPA) and operation principles. Current mode RF DAC/DPA vs. capacitive mode RF DAC/DPA – Part 2

Lecturer Bio

Ofir Degani (Senior Member, IEEE) has received the B.Sc. degree (summa cum laude) in electrical engineering and the B.A. degree in physics (summa cum laude) and the M.Sc. and Ph.D. degrees all from the Technion—Israel Institute of Technology, Haifa, Israel, in 1996, 1999, and 2005, respectively. His Ph.D. research was on MEMS inertial sensors and electrostatic actuators.

He joined the Mobility Wireless Group, Intel Corporation, Haifa, in 2006. His recent research interest includes integrated transceivers, digital transmitters, and mmWave radios in CMOS technology. He has authored or coauthored more than 80 journal articles and conference papers. He has filed more than 50 patents.

Dr. Degani was a recipient of the prestigious 2002 Graduate Student Fellowship from the IEEE Electron Devices Society and the Charles Clore Scholarship at the Charles Clore Foundation.

Guest Lecturers Bios

Assaf Ben-Bassat (Member, IEEE) received the B.Sc. and M.Sc. degrees in electrical engineering from the Technion—Israel Institute of Technology, Haifa, Israel, in 1997 and 2001, respectively, with a focus on the field of electro-optics.

From 2001 to 2003, he was with All-Optical, Haifa, developing lasers for high-speed optical communications. He joined Intel Corporation, Haifa, in 2003, where he develops circuits for baseband, RF, PLLs, and LO generation and distribution.

Shahar Gross received the B.Sc. degree in physics and the B.Sc. and M.Sc. degrees in electrical engineering from Tel Aviv University, Tel Aviv, Israel, specializing in signal processing, communication, and information theory.

In 2012, he joined as a PHY System Engineer with the Wireless Products Division, Intel Corporation, Petach-Tikva, Israel, where he is currently a PHY architect and is focused on advanced transmitter features. He took part in the Wi-Fi 6 standardization process and led the Wi-Fi PHY architecture of Intel’s first Wi-Fi 6 product.

Elan Banin received the B.Sc. degree in mechanical engineering from Tel Aviv University, Tel Aviv, Israel, in 2006.

He joined Intel Corporation, Petach-Tikva, Israel, in 2010, where he has worked as a DSP and Algorithms Engineer on multiple communication technologies.

Rotem Banin received the B.Sc. degree in electrical engineering from the Technion—Israel Institute of Technology, Haifa, Israel, in 2006, and the M.Sc. degree from Tel Aviv University, in 2015, Israel.

He joined the Mobility Wireless Group, Intel Corporation, Haifa in 2003. His recent research interest includes high-speed mixed-signal circuits and systems, integrated transceivers, digital transmitters, digital PLLs, and serial interfaces.

Ashoke Ravi (Senior Member, IEEE) received the B.Tech. degree in electrical engineering from IIT Madras, Chennai, India, and the M.S. and Ph.D. degrees in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA, USA.

In 2001, he joined Intel Corporation, Hillsboro, OR, USA, where he is currently a Principal Engineer, working on innovation projects with the Advanced Radio Technology Team. His prior contributions were in developing integrated RF transceivers on deeply scaled CMOS processes and MIMO radios. He has authored or coauthored 50 IEEE conference papers and journal articles and coauthored three book chapters. He has 35 issued patents in this field. His research interests are in RF and mixed-signal circuits and architectures for connectivity, cellular, and SoC applications. Over the last several years, these activities have included leading the research and development of mm-waveband transceivers, digital polar and outphasing transmitters, digital PLLs, and data converters.

Dr. Ravi was nominated to the MIT Technology Review’s list of top 35 young innovators (the TR35) in 2009.

Gil Asa (Ph.D.) has received B.Sc. , M.Sc. , Ph.D. (all summa cum laude, from the Technion -IIT), focusing on micro-electronics. He graduated Ph.D. at 1999 researching advanced nuclear camera and detectors. At 1998 he took part in the Technion Israeli satellite project with design of Gamma ray spectrometer, which reports supernova activities. Till 2002 he was a project leader at IBM research labs working on ultra-high speed SiGe serializers, and till 2006 he was a senior circuit designer at Marvell working on self-invented digital PLL. Till 2012 he was the founder and CTO of compact SRAM start up and till 2015 he was an analog expert consultant at Inomize, working on video camera implanted inside the eye of partially blind patients. Since 2015 he joined Intel as signal integrity leader and since 2017 the focus is on RF circuit design, digital transmitters and relevant IP development. Dr. Asa has at least 10 academic papers, and over 25 worldwide patents (10 of them as sole inventor).

Run Levinger received the M.Sc. degree (Summa Cum Lauda) in electrical and electronics engineering from Tel-Aviv University, Tel Aviv, Israel, in 2015. His research thesis focused on linearization techniques for integrated E-band transmitter circuits such as up-converting mixers and power detectors. In 2011, he joined the IBM Haifa Research Laboratories, Haifa, Israel, where he was a Research Staff Member with the mm-Wave Technologies Group. In 2016, he joined Intel’s Radio Product Development group, Petah-Tikva, Israel, where he is a senior technical staff member. His research interests include designing, measuring, and modeling of integrated RF and millimeter-wave voltage and digital controlled oscillators (VCOs and DCOs), frequency synthesizers, frequency dividers, mixers, power detectors, and passives

for communication, radar, and imaging applications. He has Authored and Co-Authored more than 25 Conference and Journal papers and holds 10 US patents with several more pending.

Evgeny Shumaker graduated B.Sc. (summa cum laude), M.Sc. (summa cum laude) and Ph.D. degrees all from the Electrical Engineering department, Technion—Israel Institute of Technology, Haifa, Israel, in 2002, 2004, and 2010, respectively. His Ph.D. dissertation focused on basic limits and applications of slow and fast light phenomenon in microwave photonics.

In 2010 he joined IBM Haifa Research Laboratory where he was a Research Staff Member, leading R&D of passive millimeter wave imaging systems. In 2015 he joined Intel’s Radio Product Development group, Haifa, Israel, where he is currently a Senior Technical Staff Member. His research interests include real-time algorithms and techniques for high precision digital frequency synthesis. He has authored or coauthored more than 40 journal articles and conference papers and filed more than 10 patents.

Dr. Shumakher is a two-time recipient of the E.I. Jury award (2004, 2009) and the prestigious Graduate Student Fellowship from the IEEE Photonics Society (2009).

Highly-Integrated Millimeter-Wave Radar Systems in Silicon-Based Technologies

February 23-25, 2020

Instructor:                    Prof. Vadim Issakov, OVGU Magdeburg, Germany

Teaching assistant:   Nimrod Ginzber (nimrodg@campus.technion.ac.il)

Lectures:                       13 hours, three days.

Academic points:       1pts

Exam:  28/02/2020 at 9:00 and/or 20/03/2020 at 9:00

 

Topics

This course will cover advanced topics in radar systems from system calculation to mm-wave circuit design and integration with antennas.

 

Prerequisites

  • 044142 | Linear Electronic Circuits or
  • 044137 | Electronic Circuits

Assignments

The course will consist of: lectures, discussion, practical examples, exam.

Course Abstract and Outline

Recent advances of silicon-based semiconductor processes and packaging technologies have accelerated the implementation of radar sensors for numerous mass-volume applications at mm-wave frequencies. CMOS and SiGe technologies seem to provide a very attractive solution for realization of mm-wave radar transceivers.

This first part of the lecture will start with the basic introduction of continuous-wave (CW) and pulsed radar systems. We discuss briefly the frequency regulations for automotive and consumer radar applications. Then we focus only on CW and FMCW systems and consider range, velocity and angular resolution. We discuss how to derive a specification of the radar system based on the specific radar application scenario, as e.g. link budget calculation, frequency chirp, dimensioning of filters and VGA in the analog baseband, choosing sampling rate and resolution of the ADC. Next, we discuss the impact of phase noise on radar systems, as e.g. range correlation effect. Further, we discuss the radar signal processing, range-Doppler map and detection of multiple targets. Finally, we discuss advanced topics as noise floor degradation by non-ideal mixing and TX to RX spillover cancellation and show integrated radar system examples. Then, we derive specification of the circuit blocks based on the system requirements and adress the design of the blocks separately in the second part.

The second part deals with the circuit design and physical implementation of the systems on chip (SoC) and systems in Package (SiP) for mm-wave radar applications. First, we repeat the basics of mm-wave design, as e.g. CMOS and bipolar transistor performance at mm-wave, passives at mm-wave, nonlinearity, noise, stability. Next, we discuss the design of mm-wave LNA, mixers (active and passive), VCO, Power Amplifier, frequency divider and multiplier. We discuss considerations on LO synthesis and distribution for large chips. Additionally, we discuss realization challenages of antenna on-chip and in package at mm-wave frequencies. Finally, we discuss examples of latest reported radar transceivers.

This course aims to provide a deep overview over modern radar systems for automotive and consumer applications. The students will get a broad scope starting from the radar sensing scenario, translating it into the block specification, designing the circuit blocks and realization of the transceivers. Novice designers can get an introduction to circuits and systems, while experienced mm-wave designers can expand their knowledge by connecting the circuits and systems for radar applications.

Course schedule:

23.02.20:

09:30-10:45 – Introduction to Radar Systems and Radar Fundamentals

10:45-11:15 – Coffee break

11:15-12:30 – Doppler Radar and Pulse Radar

12:30-13:30 – Lunch break

13:30-14:45 – FMCW Radar and Chirp-Sequence Radar

14:45-15:15 – Coffee break

15:15-16:30 – Advanced Effects in FMCW Systems

 24.02.20:

09:30-10:45 – Systematic Design Steps of FMCW Radar Systems

10:45-11:15 – Coffee break

11:15-12:30 – Specification Calculation of RF Circuit Blocks & Analog Baseband

12:30-13:30 – Lunch break

13:30-14:45 – Fundamentals of mm-wave Circuit Design

14:45-15:15 – Coffee break

15:15-16:30 – LNA Design

 25.02.20:

09:30-10:45 – Mixer Design

10:45-11:15 – Coffee break

11:15-12:30 – Power Amplifier Design

12:30-13:30 – Lunch break

13:30-14:45 – LO Generation and Distribution

14:45-15:15 – Coffee break

15:15-16:30 – Antenna on-chip and in-package and State of the Art Systems

Lecturer Bio

Vadim Issakov received the M.Sc. degree in microwave engineering from the TU Munich in 2006 and the Ph.D. degree from the University of Paderborn, Germany, in 2010. He received an award for the outstanding dissertation from the VDE (German Association of Engineers) and best dissertation award from the University of Paderborn.

In March 2010 he joined Infineon in Neubiberg, Germany. Afterwards he worked at IMEC and Intel Corporation, before he came back to Infineon in August 2015 as mm-wave Design Lead and Principal Engineer leading a research group working on pre-development of mm-wave radar and communication products. His work has been recognized by the IEEE MTT Outstanding Young Engineer Award. Since 2014 he was teaching classes on Analog RF CMOS Circuits and Highly-integrated mm-wave Circuits as Adjunct Lecturer at the University of Bochum and University of Erlangen, Germany. In September 2019 he joined the University of Magdeburg, Germany, as a full professor holding the Chair for Electronics.

Nanoscale Design Methodologies for Low-Power and Robust Gigascale

Supervisor: Prof. Volkan Kursun

Place: Technion

Date: 22.6.08

Abstract:

CIRCUIT DESIGN TECHNIQUES FOR LOW-POWER AND ROBUST NANOSCALE INTEGRATION

DAY, 1 22 June 2008

9:30-11:00    Domino logic and body biasing

11:30-13:00  Multi-Threshold circuits (MTCMOS)

14:00-15:30  Memory circuits

16:00-17:30  Power supply switching and voltage conversion circuits

DAY 2, 23 June 2008

9:30-11:00  Design techniques for variation tolerant circuits

11:30-13:00 Temperature-adaptive circuits

14:00-15:30 Designing with FinFET transistors I

16:00 – 17:30  Designing with FinFET transistors II

Volkan Kursun

Assistant Professor

Biography

Volkan Kursun received the B.S. degree in Electrical and Electronics Engineering from the Middle East Technical University, Ankara, Turkey in 1999, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from the University of Rochester, New York in 2001 and 2004, respectively.

He performed research on mixed-signal thermal inkjet integrated circuits with Xerox Corporation, Webster, New York in 2000. During summers 2001 and 2002, he was with Intel Microprocessor Research Laboratories, Hillsboro, Oregon, responsible for the modeling and design of high frequency monolithic power supplies. He has been an assistant professor in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison  since 2004.

His current research interests are in the areas of low voltage, low power, and high performance integrated circuit design, modeling of semiconductor devices, and emerging integrated circuit technologies.

Dr. Kursun is an associate editor of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the IEEE Transactions on Circuits and Systems I, the IEEE Transactions on Circuits and Systems II, and the Journal of Circuits, Systems, and Computers (JCSC) and an organizing / technical program committee member of the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), ACM/SIGDA Great Lakes Symposium on VLSI (GLSVLSI), IEEE International Symposium on Circuits and Systems (ISCAS), IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), and the IEEE/ACM International Symposium on Quality Electronic Design (ISQED).

 

Contact:

Phone: 608-262-8804

Fax: 608-262-8804

E-mail: kursun@engr.wisc

Mixed-Signal Circuit and Architecture Design for CMOS Data Converters

Supervisor: Prof. Murmann

Place: Technion

Date: 28-12-08

Abstract: 

Dates: 28-30 December 2008
Location: Meyer building, Department of electrical engineering, Technion, Haifa, Israel
This course will cover the design of mixed-signal integrated circuits for implementing the interfaces between analog and digital signals in CMOS VLSI systems. Topics include fundamental circuit elements such as comparators, track-and-hold circuits, and operational transconductance amplifiers. Architecture-specific material will focus on pipeline ADCs and current-steering DACs. The course ends with a discussion on technological limits and current research topics.
 
Sunday:
08:30-10:00, 10:30-12:00 Data converter architectures, specifications and trends; voltage comparator design
13:30-15:00, 15:30-17:00. Track-and-hold circuit design, analysis of nonidealities such as noise and distortion
Monday:
08:30-10:00, 10:30-12:00 Operational transconductance amplifiers, gm/ID based design
13:30-15:00, 15:30-17:00 Pipeline ADCs, architecture and circuit design
Tuesday
08:30-10:00, 10:30-12:00 Fundamentals of Nyquist DAC design; data converter testing
13:30-15:00, 15:30-17:00 Limits on ADC power dissipation; research topics
  
Prof. Boris Murmann, Stanford University
Short biography
Boris Murmann received the Dipl.-Ing. (FH) degree in communications engineering from Fachhochschule Dieburg, Germany, in 1994, and the M.S. degree in electrical engineering from Santa Clara University, Santa Clara, CA, in 1999. In 2003, he received the Ph.D. degree in electrical engineering from the University of California at Berkeley.
From 1994 to 1997, he was with Neutron Mikrolektronik GmbH, Hanau, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. During 2001 and 2002, he held summer positions with the High-Speed Converter Group at Analog Devices, Wilmington, MA. Since 2004, he has been an Assistant Professor in the Department of Electrical Engineering, Stanford, CA. His research interests are in the area of mixed-signal integrated circuit design, with special emphasis on data converters and sensor interfaces.
At UC Berkeley, Dr. Murmann received the outstanding graduate student instructor award in 1999 and the CalView award for excellence in distance education in 2003. He was a co-recipient of the Meritorious Paper Award at the 2005 US Government Microcircuit & Critical Technology Conference. Dr. Murmann served as a guest editor for the EURASIP Journal on Advances in Signal Processing in 2007. He currently serves as a member of the International Solid-State-Circuits Conference (ISSCC) program committee.

Course Material

 

Low Power CMOS Circuit Design

Supervisor: Professor Yusuf Leblebici

Place: Auditorium Floor 10, Electrical Engineering Building, Technion

Date: 12-14 October 2009

Abstract: 

Seminar “Low Power CMOS Circuit Design”

12-14 October 2009

Professor Yusuf Leblebici

Yusuf Leblebici received the B.S. and M.S. degrees in electrical engineering from Istanbul Technical University in 1984 and 1986, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990.

 

Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI), where he established and directed the VLSI Design Laboratory, and also served as a project director at the New England Center for Analog and Mixed-Signal IC Design. He also worked as the Microelectronics Program Coordinator at Sabanci University. Since January 2002, he has been a full professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of the Microelectronic Systems Laboratory. His research interests include design of high-speed and low-power CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, modeling and simulation of nano-electronic circuits, intelligent sensor interfaces, and VLSI reliability analysis. Dr. Leblebici is the coauthor of three textbooks, namely, “CMOS Digital Integrated Circuits: Analysis and Design” (McGraw Hill, 1996, 1999 and 2003), “Hot-Carrier Reliability of MOS VLSI Circuits” (Kluwer Academic, 1993), “CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications” (Springer, 2007) as well as more than 150 scientific articles published in international journals and conferences.

 

Dr. Leblebici has served on the organizing and technical program committees of the 1995 European Conference on Circuit Theory and Design (ECCTD 1995), the 2004 European Workshop on Microelectronics Education (EWME 2004), and as General Co-Chair of the Joint 2006 European Solid-State Circuits Conference and European Solid-State Device Research Conference (ESSCIRC-ESSDERC 2006). He also served as an Associate Editor of IEEE Transactions on Circuits and Systems II, and as an Associate Editor of IEEE Transactions on VLSI. He received the Young Scientist Award of the Turkish Scientific and Technological Research Councils in 1995, and the Joseph Samuel Satin Distinguished Fellow Award of the Worcester Polytechnic Institute in 1999.

 

Syllabus

Low Power CMOS Circuit Design

  1. Introduction to low power CMOS circuit design
    2. Dynamic (switching) and leakage power consumption
    3. Influence of technology scaling and nanometer CMOS
    4. Minimizing energy consumption under performance constraints
    5. Dynamic voltage-frequency scaling (DVFS) techniques
    6. Physics and modeling of subthreshold operation in MOSFETs
    7. CMOS logic operating in subthreshold regime
    8. Benefits and limitations of subthreshold operation in view
    of increased leakage in nanometer CMOS technologies
    9. Current mode operation for low power
    10. Subthreshold source-coupled logic (STSCL) circuits
    11. Complex logic gates using STSCL style
    12. Two-phase pipelining to improve activity rate
    13. Source-follower buffer drivers for large fanout
    14. Design automation for standard-cell based STSCL design
    15. Cell library creation, placement & routing techniques

 

Agenda

 

Monday 12.10.09

 

13:00 – 13:30 Registration

13:30 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 18:00 lecture

 

Tuesday 13.10.09

 

08:30 – 09:00 Coffee

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

 

Wednesday, 14.10.09

 

08:30 – 09:00 Coffee

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

 

Admission

Admission to the course is free of charge only to Members of the ACRC,

Brief RFIC seminar

Supervisor: Prof. Avinoam Kolodny

Place: Auditorium Floor 10, Electrical Engineering Building, Technion

Date: 25.1.10

Abstract:

Brief RFIC seminar

25.1.10

Floor 10, Room1007 Electrical Engineering Building, Technion

 

 

13:30 – 13:45 Reception & Light Refreshments

 

14:00 – 14:30 Dr. Christopher D. Hull

RF transceiver from 3.x towards 4G/ OFDM based systems

 

14:30 – 15:00 Dr. Ofir Degani

Past present and future CMOS Power amplifiers for Wireless

Communications

 

15:00 – 15:30 Coffee Break

 

15:30 – 16:00 Mr. Emanuel Cohen

60 GHz system and components in CMOS for low power compact

Phase Array applications Open discussion- 30 min

 

16:00 – 16:30 Discussion

 

Power Supply Issues in VLSI Systems

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 18.7.10

Abstract:

ACRC Workshop on Challenges and Recent Research in On-Chip Power Delivery

July 18, 2010
Technion, EE building, Auditorium 1003 (10th floor)

Goals: The core issues in on-chip power delivery will be discussed, and related research problems outlined. Some examples of specific research results in the area of on-chip DC-DC conversion and algorithms for efficient IR drop analysis will also be described.
Participants: Engineers from ACRC companies, graduate students and researchers engaged in various aspects of power supply subsystems (e.g. voltage conversion, regulation, on-chip power delivery, power management).

Agenda:
09:30 – 10:00   Registration and refreshments
10:00 – 10:45   Prof. Eby Friedman (Technion)
Introduction/Tutorial: Challenges of Power Delivery
in VLSI Systems
.
10:45 – 11:15   Dr. Michael Zelikson (Intel)
System-on-Chip Power Delivery Management – Goals,
Trends and Issues.
The main principles of a modern power delivery
system, possible development directions, anticipated
challenges and interes/files/2018/06/Challenges-of-Integrated-Systems-Power-Delivery-Management_-back.pdfting research directions.
Integrated Circuit Power Management Platforms incorporate
logic and analog blocks together with high voltage and
current power drivers on the same chip. This combination
allows serving a host of applications ranging from power
management in portable devices, power delivery in computer
motherboards through dc dc motor drives and to LED drivers
in street lighting and TV screens.
12:00 – 12:30   Eitan Rosen (Marvell)
Local and Global Investigation of On-chip Power
Simulations of Local and Global Power issues enable understanding
of issues and Power grid and de-coupling capacitors methodology
development.

12:30 – 13:00  Nimrod Ben Ari (Zoran)
 Zoran On-chip Distributed Power Switch

Zoran Power Switch methodology and implementation, including
supporting peripheral circuits, And silicon results.

13:00 – 13: 30   Lunch Break

13:30 – 14:00   Gregory Sizikov (Intel)
Efficiency Considerations for On-chip DC-DC Buck Converters
An analytic method to evaluate frequency dependent losses in on-chip
DC-DC buck converters will be described. The analytical model will
be used for optimizing switching frequency and for minimizing losses
at light and heavy loads.

14:00 – 14:30   Dr. Aharon Unikovsky (Tower)
 A bandgap reference circuit for wide voltage range applications

A bandgap circuit that works in a voltage range of 4V up to 42V
with a very low current consumption and high PSRR.

14:30 – 14:45   Coffee Break

15:00 – 16:00
   Panel/Brainstorming session: Open research problems and development directions in VLSI power supply management

16:00 – 16:15   Conclusion

You are invited to a guest lecture after the seminar:
16:30-17:30 Dr.Ingmar Kallfass
The use and benefit of modern active millimeter-wave monolithic integrated circuit (MMIC) technology in high resolution sensing, imaging and high data rate wireless communication applications will be discussed. State-of-the-art in millimeter-wave low-noise and solid-state power amplification is briefly covered. Examples of MMICs based on state-of-the-art metamorphic high electron mobility transistor (mHEMT) technology with gate lengths down to 35 nm and cutoff frequencies fT of over 500 GHz and fmax of more than 700 GHz will be presented. A focus is on the multifunctional integration of analog frontend receivers and transmitters as well as frequency multipliers covering the entire millimeter-wave range up to and beyond 300 GHz. Furthermore, an ongoing Technion – Fraunhofer cooperation in the field of high-speed analog-to-digital converters based on InP hetero-bipolar transistor technology is introduced.

Variation and Low Voltage Digital Circuit Design

Supervisor: Professor David Harris

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 30.12.10

Abstract:

Variation and Low Voltage Digital Circuit Design

Professor David  Harris

  Dep. of Engineering Harvey Mudd College in Claremont, CA.

30.12.10

Auditorium floor 10

This course addresses the challenges of nanometer circuit design arising from variation and low-voltage operation.  The course begins with a review of the sources of variation and the impact on delay, energy, and functionality.  It examines back-of-the envelope statistical analysis techniques to rapidly assess the impact of variation.  Variation effects are accentuated for circuits running at low voltage, particularly in applications such as embedded sensing and dynamic voltage scaling where energy efficiency is critical.  The course describes methods and limits of low-voltage circuit design, including combinational logic, registers, and SRAM design.  Resilient sequencing elements such as Razor and DSTB are particularly interesting because they can reduce the guard bands required to accommodate variation in DVS systems.

 

David  Harris is a Professor of Engineering at Harvey Mudd College in

Claremont, CA.  Prof. Harris received his Ph.D. from Stanford University and his S.B. and M.Eng. degrees from MIT. He has designed circuits at Intel, Hewlett-Packard, Sun Microsystems, and elsewhere.

His research interests include high-performance and low-power digital circuit design, arithmetic, and microprocessors.  Prof. Harris is the co-author of CMOS VLSI Design, Logical Effort, and two other books in the field.

Agenda

08:30 – 09:00 Registration

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

The seminar is free of charge to ACRC members, Intel, Zoran, Marvell, Mellanox.

Others will be charged 500 Shekels+VAT for participating in the seminar.

Course Material

Analog and Mixed-signal Integrated Circuit Design

Supervisor: Prof. Zeljko Ignjatovic

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 15.2.11

Abstract:

Analog and Mixed-signal Integrated Circuit Design

Can we describe analog and mixed-signal circuits as telecommunication channels and determine fundamental limits utilizing Information theory tools?

Professor Zeljko Ignjatovic, University of Rochester

15-17.2.11

Technion, EE building, Auditorium 1003 (10th floor)

Academic organizers:  Prof. Eby Friedman and Prof. Avinoam Kolodny

Please, Register Online!

Course description and material: This course will discuss the circuitry, algorithms and architectures used in analog and mixed-signal mode CMOS integrated circuits, provide practical considerations and detailed design examples . In addition, information theoretical concepts closely related to the design of A/D converters will be discussed and their fundamental resolution-bandwidth limits will be presented. The discussion of the following topics is planned:

Agenda

February 15th

 

08:30 – 09:00 Registration

09:00 – 10:30 Introduction to Switched Capacitor (SC) Circuits and basic building blocks

10:30 – 10:45 Coffee Break

10:45 – 13:00 First order and biquad SC filters

13:00 – 14:00 Lunch Break

14:00 – 15:30 High-order SC filters and Non-ideal effects

15:30 – 15:45 Coffee Break

15:45 – 17:00 Other SC stages and Introduction to Sigma-delta A/D converters

February 16th

 

09:00 – 10:30 Noise shaping, MASH structurs and Non-ideal effects

10:30 – 10:45 Coffee Break

10:45 – 13:00 Higher order Sigma-delta Topologies

13:00 – 14:00 Lunch Break

14:00 – 15:30 Spread-spectrum Technique in Sigma-delta ADC

15:30 – 15:45 Coffee Break

15:45 – 17:00 Noise in SC circuits and Sigma-delta ADC; Turbo-code A/D converters

February 17th

 

09:00 – 10:30 CMOS Image Sensors

10:30 – 10:45 Coffee Break

10:45 – 13:00 Pixel designs in CMOS image sensors

13:00 – 14:00 Lunch Break

14:00 – 15:30 Image sensor readout methods with global feedback – improving readout speed and noise

15:30 – 15:45 Coffee Break

15:45 – 17:00 Fully digital image sensors utilizing pixel level Sigma-delta A/D converters

 

The seminar is free of charge to ACRC members, Intel, Marvell, Mellanox, Samsung, Zoran.

Others will be charged 1500 Shekels+VAT for participating in the seminar.

The course is open free of charge for EE students (undergraduate and graduate).