047003 – All-Digital Phase-Locked Loops (ADPLL)
October 19,20,23 2022
Auditorium 1003, Mayer Bld.
Professor Robert Bogdan Staszweski, University College Dublin, Ireland
| Instructor: | Prof. Robert Bogdan Staszweski |
| Teaching assistant: | Itamar Melamed |
| Lectures: | 13 hours, 3 days |
| Academic points: | 1pts |
| Exam: | TBD |
| Course Fee : | 1700$ (see membership options) |
*Registration is open until August 18, 2022
Course Content:
The past two decades has seen proliferation of all-digital phase-locked loops (ADPLL) for RF and highperformance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer
function precision, settling speed, frequency modulation capability, and amenability to integration with
digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also
exhibits advantages of better performance, lower power consumption, lower area and cost over the
traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced
by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional
phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for
detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an
analog loop RC filter got replaced with a digital loop filter. The conversion gains of the DCO and TDC circuits
are readily estimated and compensated using “free” but powerful digital logic.
Topics per Day:
Days 1 & 2: (7 academic hours) All-Digital Phase-Locked Loop (ADPLL)
Architecture and Implementation
This lecture presents a system-level view of the ADPLL.
1. Principles of phase-domain frequency synthesis
2. ADPLL closed-loop behavior
3. Direct frequency modulation of ADPLL
4. Alternative TX architectures using ADPLL and PA regulator
5. Survey of published ADPLL architectures; TDC-less ADPLL; cell-based ADPLL design
Day 3 Morning (3 academic hours): Digitally-controlled oscillator (DCO)
A digitally controlled oscillator (DCO) lies at the heart of an all-digital phase-locked loop (ADPLL). It is based
on an LC-tank with a negative resistance to perpetuate the oscillation— just like the traditional VCO, but
with a significant difference in one of the components: instead of continuously tuned varactor (variable
capacitor), the DCO now uses a large number of binary-controlled varactors. Each varactor can be placed
in either high or low capacitative state. The composite varactor performs digital-to-capacitance
conversion. This lecture presents a circuit and system level views of DCO.
Day 3 Afternoon (3 academic hours): Time-to-digital converter (TDC)
A time-to-digital converter (TDC) is used in the ADPLL to perform the phase detection. It generates a digital
variable phase or timestamps of the FREF edges in the units of the DCO clock period. The variable phase
is a fixed-point digital word in which the fractional part is measured with a resolution of an inverter delay
(about 10 ps in 40-nm CMOS). This lecture presents a system level view of TDC as well as its circuit-level
implementation issues.
Prerequisites:
- 044137 Electronic Circuits
- 044202 Random Signals
Grading:
Written exam – 100%
Recommended Literature and Study Materials:
Book: R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep-Submicron CMOS, New
Jersey: John Wiley & Sons, Inc., Sept. 2006. ISBN: 978-0471772552.
Instructor’s Bio:
Robert Bogdan Staszewski received the BSc (summa cum laude), MSc and PhD degrees from the University
of Texas at Dallas in 1991, 1992 and 2002, respectively. From 1991 to 1995 he was with Alcatel Network
Systems in Richardson, TX, USA, working on SONET cross-connect systems for fiber optics
communications. He joined Texas Instruments in Dallas, TX, USA, in 1995 where he was elected
Distinguished Member of Technical Staff (2% of the technical population). Between 1995 and 1999, he
was engaged in advanced CMOS read channel development for hard disk drives. In 1999 he co-started a
Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally intensive
approaches to traditional RF functions for integrated radios in deep-submicron CMOS. He served as a CTO
of the DRP group between 2007 and 2009. In 2009, he joined Delft University of Technology in the
Netherlands where he is currently a guest Full Professor. Since 2014, he has been a Full Professor with
University College Dublin in Ireland. He has authored and co-authored seven books, 11 book chapters,
160 journal and 220 conference publications, and holds 220 issued US patents. His research interests
include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers,
as well as quantum computers. He is an IEEE Fellow and recipient of IEEE Circuits and Systems Industrial Pioneer Award.
*Registration is open until August 18, 2022