Variation and Low Voltage Digital Circuit Design

Supervisor: Professor David Harris

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 30.12.10


Variation and Low Voltage Digital Circuit Design

Professor David  Harris

  Dep. of Engineering Harvey Mudd College in Claremont, CA.


Auditorium floor 10

This course addresses the challenges of nanometer circuit design arising from variation and low-voltage operation.  The course begins with a review of the sources of variation and the impact on delay, energy, and functionality.  It examines back-of-the envelope statistical analysis techniques to rapidly assess the impact of variation.  Variation effects are accentuated for circuits running at low voltage, particularly in applications such as embedded sensing and dynamic voltage scaling where energy efficiency is critical.  The course describes methods and limits of low-voltage circuit design, including combinational logic, registers, and SRAM design.  Resilient sequencing elements such as Razor and DSTB are particularly interesting because they can reduce the guard bands required to accommodate variation in DVS systems.


David  Harris is a Professor of Engineering at Harvey Mudd College in

Claremont, CA.  Prof. Harris received his Ph.D. from Stanford University and his S.B. and M.Eng. degrees from MIT. He has designed circuits at Intel, Hewlett-Packard, Sun Microsystems, and elsewhere.

His research interests include high-performance and low-power digital circuit design, arithmetic, and microprocessors.  Prof. Harris is the co-author of CMOS VLSI Design, Logical Effort, and two other books in the field.


08:30 – 09:00 Registration

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

The seminar is free of charge to ACRC members, Intel, Zoran, Marvell, Mellanox.

Others will be charged 500 Shekels+VAT for participating in the seminar.

Course Material