Category: Event

ACRC Seminar: High-Speed CMOS Silicon Photonic PAM4 Transceiver Front-Ends for Datacenter Communication by Prof. Samuel Palermo, Texas A&M University

Title: High-Speed CMOS Silicon Photonic PAM4 Transceiver Front-Ends for Datacenter Communication
Speaker: Prof. Samuel Palermo, Texas A&M University
Date: March 05, 2026 – Thursday
Time: 11:30 – 12:30 Israel Time
Location: Room 608 Zisapel Building (New), Technion
Language: English
Abstract:
Growing interconnect bandwidth demand in large datacenters requires energy-efficient optical transceivers that operate with four-level pulse amplitude modulation (PAM4) to enable high per-wavelength data rates. Further increases in bandwidth density is possible by leveraging wavelength-division multiplexing (WDM), which optical link architectures based on silicon photonic microring modulators (MRMs) and drop filters inherently enable. This talk covers high-speed PAM4 transmitter and receiver front-ends implemented in a 28nm CMOS process that are co-designed with these silicon photonic optical devices to enable energy-efficient operation. The transmitter utilizes an optical digital-to-analog converter (DAC) approach with two PAM2 AC-coupled pulsed-cascode high-swing voltage-mode output stages to drive the MRM MSB/LSB segments. A 3.42Vppd output swing is achieved when operating at 80Gb/s PAM4 with an energy efficiency of 3.66pJ/bit. The optical receiver utilizes a low-bandwidth input transimpedance amplifier followed by continuous-time linear equalizer, variable-gain amplifier stages, and a digital clock-and-data recovery system. 100Gb/s PAM4 operation is achieved with -6.4dBm sensitivity at 1.4×10-4 BER and 1.32pJ/bit energy efficiency.
Bio: 
Samuel Palermo (S’98-M’07-SM’17) received the B.S. and M.S. degrees in electrical engineering from Texas A&M University, College Station, TX in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA in 2007. From 1999 to 2000, he was with Texas Instruments, Dallas, TX, where he worked on the design of mixed-signal integrated circuits for high-speed serial data communication. From 2006 to 2008, he was with Intel Corporation, Hillsboro, OR, where he worked on high-speed optical and electrical I/O architectures. In 2009, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently the J. W. Runyon Jr. Professor. His research interests include high-speed electrical and optical interconnect architectures, RF photonics, radiation-hardened electronics, and AI computing hardware. Dr. Palermo is a recipient of a 2013 NSF-CAREER award. He is a member of Eta Kappa Nu and IEEE. He is currently an associate editor for IEEE Journal of Solid-State Circuits and has previously served in this role for IEEE Solid-State Circuits Letters and IEEE Transactions on Circuits and System – II. He has also previously served as a distinguished lecturer for the IEEE Solid-State Circuits Society and on the IEEE CASS Board of Governors. He was a coauthor of the Jack Raper Award for Outstanding Technology-Directions Paper at the 2009 International Solid-State Circuits Conference, the Best Student Paper at the 2014 Midwest Symposium on Circuits and Systems, an Outstanding Student Paper Award at the 2018 Custom Integrated Circuits Conference, and the Best Student Paper Award at the 2024 Opto-Electronics and Communications Conference. He received the Texas A&M University Department of Electrical and Computer Engineering Outstanding Professor Award in 2014 and the Engineering Faculty Fellow Award in 2015.

ACRC Webinar: Radiation Hardening By Design

Speaker: Tuvia Liran

Date: February 16, 2026 – Monday

Time: 16:00 – 17:30 Israel Time

Language: Hebrew

Register Here

Abstract:

Chips are exposed to energetic particles, but in some applications, such as space, the doze of particles is high and hazardous. Protons, ion, neutrons, alpha/beta/gamma particles and X-ray might degrade the performance, shorten lifetime, and might cause hard or soft failures.

The lecture will describe the failure mechanisms and key mitigation techniques. The common mechanisms are TID, SEL, SEU, but there are additional mechanisms that might affect special applications. It is typically not practical to eliminate the failures, but it is practical and achievable to mitigate them significantly.

Mitigation the radiation effects can be done by process, architecture/logic/circuit/layout design, by software/firmware, and by system level mechanical/hardware/software techniques. The key techniques will be presented. The most common mitigation technique, which is implemented during the chip design flow, is named Radiation Hardening By Design (RHBD). This is the main scope of the lecture.

Advanced semiconductor technologies are inherently more immune to radiation effects. However, some circuits, especially those operate at relatively high voltage, might be under-protected, unless mitigated by simple design techniques. Some tips will be provided.

Bio:

Tuvia Liran had >40 years of experience in VLSI development, including analog & digital design, process, testing, Q&R, packaging and more. He wrote 15 patents, mostly on VLSI circuits.
He graduated Bsc in physics, and EE and Msc in electronics from the Technion in the eighties, and since then he was in VLSI industry, and mentoring projects in VLSI lab.
He was co-founder of Ramon.Space, where he was responsible, as CTO, for the development of the technologies for space applications. The components demonstrated extremely high immunity to all radiation effects, and company’s products had been selected for many space missions, including missions to Mars, Asteroids, Jupiter, Saturn, Sun, and many satellites.

He served as navigator in IAF during his military service.

The webinar is free but registration is required. The Zoom link will be sent after registration.

Register Here

ACRC Webinar: “Spiking Manifesto” – a new way to build and train artificial neural networks

Date: February 11, 2026 – Wednesday

Time: 17:00 – 18:30 Israel Time

Speaker: Eugene Izhikevich, Founder and CEO of SpikeCore

Language: English

Register Here

Abstract: 

Current AI models are a thousand times less energy-efficient than the brain. These models use artificial neural networks (ANNs) requiring GPUs for multiplication of huge matrices. In contrast, spiking neural networks (SNNs) within the human brain do not employ matrix multiplication and dissipate orders of magnitude less energy.

In this talk, Prof. Eugene Izhikevich presents the Spiking Manifesto: a framework for thinking about popular AI models in terms of spiking networks and polychronization, and for interpreting spiking activity within the brain as nature’s way of providing look-up tables. This approach offers a novel approach to develop ANNs in hardware and to build AI models based on innovative architectures. The spiking manifesto provides a path to thousandfold improvements in energy efficiency.

Biography: 

Founder and CEO of SpikeCore, San Diego, California
Founder and Chairman of the Board of Brain Corp, San Diego, California
Founder and Editor-in-Chief of Scholarpedia – the peer-reviewed encyclopedia
Publications: https://scholar.google.com/citations?user=1JeBX-IAAAAJ

The webinar is free, but registration is required. The Zoom session link will be sent after registration. 

Register Here

ACRC Webinar: Quantum Supercomputers

Title: Quantum Supercomputers
Speaker: Dr. Yonatan Cohen, Co-founder and CTO of Quantum Machines
Date: January 13, 2026, Tuesday
Time: 16:00 Israel Time
Abstract: 
Quantum computing represents a paradigm shift in how we process information, leveraging the principles of quantum mechanics to solve problems that are intractable for classical systems. In this talk, we will begin by exploring the theoretical foundations of quantum computation—how qubits, superposition, and entanglement enable exponential computational power. We will then transition to the practical aspects of building quantum computers, examining the engineering challenges and innovations that make these systems possible. Next, we will introduce the work we do at Quantum Machines, where we develop advanced control and orchestration solutions that enable and accelerates the development of useful quantum computers as well as bridge the gap between quantum and classical computing. We will discuss our vision for hybrid architectures and how these technologies pave the way toward scalable quantum supercomputers, unlocking unprecedented capabilities for science and industry.
Biography: 
Yonatan Cohen is the Co-founder and CTO of Quantum Machines (QM), the global leader in hybrid classical-quantum control solutions. An entrepreneur and physicist specializing in quantum electronics and advanced microfabrication, he previously co-founded and served as Managing Director of the Weizmann Institute of Science’s flagship entrepreneurship program, where he helped researchers translate deep-tech breakthroughs into commercial ventures. Yonatan completed his MSc and PhD in Prof. Moty Heiblum’s laboratory at the Weizmann Institute, conducting research on quantum electronics, superconducting–semiconducting hybrid devices, and nanoscale fabrication. His work has been published in leading peer-reviewed journals. He holds a BSc in Physics and Mathematics from the University of Washington and is a recipient of the Ruth and Prof. Abraham (Edek) Blaugrund Prize for Academic Excellence (2018).

A link to the Zoom session will be provided after registration.  

Important: Participation is free of charge, but registration is required.

ACRC Retreat 2026

Dear ACRC colleagues,

We are pleased to invite you to the ACRC Research Retreat 2026, which will take place on February 24–25, 2026, at Pastoral Kfar Blum Hotel.
The retreat brings together industry researchers, faculty members, and graduate students in hardware engineering for two days of technical exchange, research presentations, and cross-disciplinary discussions.
Following last year’s positive feedback, this year’s program will include additional time for discussions and meaningful interactions among participants.

Photo album from last year’s retreat – ACRC retreat 2025

Theme of the 2026 Retreat

Breaking Barriers in Scalable Computing Platforms: Energy, Connectivity, Security & Education

As AI workloads continue to reshape modern computing, scalable hardware platforms face new and complex challenges.
This year, we will focus on four domains that are defining the direction of innovation in our field:

  • Energy Efficiency
    Low-power design, sustainable computing, edge AI, In Meomry Computing
  • Connectivity & High-Speed Data Movement
    Chiplets, die-to-die, wireline, photonics, wireless beyond 5G.
  • Hardware Security for AI Systems
    Secure architectures, confidential computing, resilience to attacks.
  • Engineering education in the AI era
    Skills, workflows, AI-assisted design, academy–industry collaboration.

These themes reflect insights raised throughout the year in joint academic–industry discussions and advisory council meetings.
Detailed agenda will be published 5 weeks prior to the event.

Why Attend?

  • Engage with cutting-edge research in scalable computing platforms.
  • Participate in in-depth technical discussions with leading experts.
  • Explore opportunities for collaboration between academia and industry.
  • Contribute to shaping the next generation of hardware engineers.
  • Enjoy extended networking and informal interactions in a relaxed environment.

Program Highlights

  • Keynote lectures by leading researchers
  • Research talks from academia and industry
  • Graduate student flash talks and poster sessions
  • Roundtable discussions on emerging challenges
  • Excursion in the Upper Galilee region
  • Extended mingling and connection-building opportunities

Practical Details

  • Dates: February 24–25, 2026
  • Location: Pastoral Kfar Blum Hotel
  • Registration deadline: February 4, 2026
  • Participants: Industry researchers, faculty members, graduate students
  • Cost:
    • ACRC members receive 2-4 invitations at no cost, depending on their membership level
    • 600 NIS per faculty member
    • 300 NIS per graduate student
    • 1800 NIS per all other participants
  • Cancellation policy: Free cancellation up to one week before the event.

Registration link – Registration for the ACRC Research Retreat 2026

For additional information, please contact Ofira Levanon – levanon.o@technion.ac.il

Warm regards,
ACRC research retreat team
Prof. Ariel Cohen,
Prof. Shahar Kvatinsky
Tami Sasporta
Ofira Levanon

ACRC Course: High-Speed DSP/DAC/ADC-Based Wireline Transceivers

Instructor: Prof. Samuel Palermo, Texas A&M University
Teaching Assistant: TBD
Lectures: 3 days
Academic Points: 1
Exam: TBD
Course Fees: 1700$ (See membership options)

For registration, click here

Registration closes on February 26th, 2026

Date: March 8 – 10, 2026

Time: 9:00 – 18:00 Israel Time

Location: Auditorium 1003, Meyer Building, Technion

Language: English

Bio:

Samuel Palermo (S’98-M’07-SM’17) received the B.S. and M.S. degrees in electrical engineering from Texas A&M University, College Station, TX in 1997 and 1999, respectively, and the Ph.D. degree in electrical engineering from Stanford University, Stanford, CA in 2007. From 1999 to 2000, he was with Texas Instruments, Dallas, TX, where he worked on the design of mixed-signal integrated circuits for high-speed serial data communication. From 2006 to 2008, he was with Intel Corporation, Hillsboro, OR, where he worked on high-speed optical and electrical I/O architectures. In 2009, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently the J. W. Runyon Jr. Professor. His research interests include high-speed electrical and optical interconnect architectures, RF photonics, radiation-hardened electronics, and AI computing hardware. He is currently an associate editor for IEEE Journal of Solid-State Circuits and has previously served in this role for IEEE Solid-State Circuits Letters and IEEE Transactions on Circuits and System – II. He has also previously served as a distinguished lecturer for the IEEE Solid-State Circuits Society and on the IEEE CASS Board of Governors.

Course Content

Syllabus:

This course covers system and circuit design techniques of high-speed SERDES transceivers based on DSP, DAC, and ADC blocks. Topics include wireline channels, communication techniques, transmitters, receivers, high-speed digital-to-analog and analog-to-digital converters, equalizers, and clocking circuitry. This course is intended for Analog/Mixed-Signal IC designers and graduate students interested in learning design techniques for state-of-the-art SERDES transceivers used in datacenters, AI systems and communication systems.

Learning Outcomes:

Upon successful completion of the course, the student will be able to:

  1. Understand high-speed wireline channel properties and communications techniques
  2. Understand link system design utilizing statistical bit-error-rate analysis and modeling tools.
  3. Understand the design specifications and implementation details of high-speed SERDES circuits such as drivers, receivers, equalizers, and clocking systems
  4. Understand the design specifications and implementation details of high-speed digital-to-analog and analog-to-digital converters

Schedule:

Day 1 Morning

9-9:50 Introduction

  1. Introduction
  2. Analog Wireline Transceivers
  3. Long Reach (LR) DAC/ADC-DSP Transceivers
  4. High-Performance Data Converters

10-10:50 Wireline Channel Components and Communication Techniques

  1. 200+ Gb/s LR Channel Environment
  2. S-parameter Channel Example
  3. ISI, Pulse Response, and Peak Distortion Analysis
  4. System Noise Modeling

11-12 Equalization System Analysis

  1. TX FFE
  2. RX FFE
  3. CTLE
  4. DFE

Day 1 Afternoon

13-13:50 Wireline Transmitter Circuits

  1. Current and Voltage-Mode Drivers
  2. Swing Enhancement Techniques

14-15:15 Wireline Transmitter Circuits

  1. Analog FFE TX
  2. Impedance Control

15:30-17 Wireline Transmitter Circuits

  1. Pad Bandwidth Extension
  2. High-Speed Serializers
  3. Predriver Bandwidth Extension

17:10-18 High-Speed DAC & Digital FFE

  1. Current-Mode DAC TX
  2. Voltage-Mode DAC TX
  3. Digital TX FFE

Day 2 Morning

9-9:50 Wireline Receiver Circuits

  1. Receiver Front-End Architecture
  2. Input Bandwidth Extension Networks
  3. Low-Frequency Equalization

10-10:50 Wireline Receiver Circuits

  1. Continuous-Time Linear Equalizers
  2. Variable Gain Amplifiers
  3. AFE Linearity

11-12 Wireline Receiver Circuits

  1. Clocked Comparators
  2. Analog Link Sensitivity Analysis
  3. Deserializers

Day 2 Afternoon

13-13:50 RX Analog FFE, DFE, and Equalization Adaptation

  1. RX FFE
  2. Decision Feedback Equalizer
  3. Equalization Adaptation Techniques

14-15:15 High-Speed Time-Interleaved ADCs

  1. ADC/DSP-Based Receiver Motivation
  2. ADC Resolution Requirements & Topologies
  3. Sampling Circuits

15:30-17 ADC Circuits

  1. SAR ADC Circuits
  2. Flash ADC Circuits

17:10-18 Time-Interleaved ADC Calibration Techniques

Day 3 Morning

9-9:50 Digital RX Equalization

  1. Digital FFE
  2. Digital DFE
  3. MLSD

10-10:50 PLL Clock Generation

  1. PLL Overview
  2. Analog Charge Pump PLL

11-12 PLL Clock Generation

  1. Digital PLL
  2. Time Domain Modeling

Day 3 Afternoon

13-13:50 Wireline PLL Examples

14-15:15 Clock Distribution, Multi-Phase Generation/Calibration, and CDR Overview

  1. Clock Distribution
  2. Multi-Phase Generation
  3. Multi-Phase Calibration
  4. CDR Overview

15:30-17 Clock and Data Recovery Systems

  1. Phase Detectors
  2. Analog PLL-based CDR
  3. Digital PLL-based CDR
  4. Dual-Loop CDRs
  5. PIs & DLLs
  6. Jitter Transfer, Generation, and Tolerance

17:10-18 Alternative SERDES Transceivers – Looking Forward

  1. 100+ Gb/s LR Transceiver Trends
  2. Higher-Order PAM
  3. Simultaneous Bidirectional
  4. Discrete Multitone
  5. Multicarrier
  6. Co-Packaged Optics

Bonus Material

PLL Building Blocks

  1. PFD
  2. Charge Pump
  3. Loop Filter
  4. Time-to-Digital Converters
  5. VCOs & DCOs
  6. Dividers

For registration, click here

ACRC Webinar: Ask Me Anything & How to Write a Strong SSCS Conference Paper

Date: December 10, 2025, Wednesday

Time: 17:00 – 18:00 Israel Time

Speaker: Keith Bowman, Qualcomm Technologies

Language: English

Register Here

Abstract: 

As a follow up to the ACRC Webinar on Dec. 8th, this session provides an additional question and answer opportunity for attendees from university or industry to ask about a wide range of topics such as future technology directions, performing research in industry, transferring research ideas into products, etc.  Since some common questions from previous sessions relate to writing a Solid-State Circuits Society (SSCS) conference paper, this webinar covers this topic with a 20-minute presentation, covering the SSCS conference basics, the paper-rating criteria as presented at the IEEE International Solid-State Circuits Conference (ISSCC) Reviewer Training, and the key steps for organizing and writing a strong SSCS conference submission.

Biography:

Keith A. Bowman is a Principal Engineer and Director of the System-on-Chip Research Lab at Qualcomm Technologies, Inc. in Raleigh, NC.  He directs the research and development of circuit and system technologies to improve the performance, energy efficiency, yield, reliability, and security of Qualcomm processors.  Dr. Bowman and his team pioneered four commercially successful circuit and system solutions, significantly benefiting CPUs, GPUs, neural processing units (NPUs), and secure processing unit (SPUs) across internet-of-things (IoT), mobile, laptop, and automotive platforms.  He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering.  His career includes a 12-year tenure at Intel Corporation in Hillsboro, OR prior to joining Qualcomm in 2013.

Dr. Bowman has published over 90 technical papers, received more than 100 patents, and given over 50 tutorial, special-session, and keynote presentations.  His contributions have been recognized with the 2016 Qualcomm Corporate Research and Development (CRD) Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, and the 2022 Qualcomm IP Achievement Award.  He has held various leadership roles within the IEEE Solid-State Circuits Society (SSCS) such as serving as an IEEE SSCS Distinguished Lecturer, IEEE SSCS Mentor, and multiple technical committee positions for the IEEE International Solid-State Circuits Conference (ISSCC).  He currently serves as the ISSCC 2026 Program Chair.  He is a Fellow of the IEEE.

The webinar is free, but registration is required. The Zoom link will be sent after registration.

Register Here

ACRC Webinar: Adaptive Processor Designs

Date: December 8, 2025, Monday

Time: 16:00 – 17:30 Israel Time

Speaker: Keith Bowman,  Qualcomm Technologies

Language: English

Register Here

Abstract: 

System-on-chip (SoC) processors across a wide range of market segments, including Internet of Things (IoT), mobile, laptop, automotive, and datacenter, experience dynamic device, circuit, and system parameter variations during the operational lifetime.  These dynamic parameter variations, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations, degrade processor performance, energy efficiency, yield, and reliability.  This webinar introduces the primary variation sources and the negative impact of these variations across voltage and clock frequency operating conditions.  Then, this webinar presents adaptive processor designs to mitigate the adverse effects from dynamic parameter variations while highlighting the key trade-offs and considerations for product deployment.

Biography:

Keith A. Bowman is a Principal Engineer and Director of the System-on-Chip Research Lab at Qualcomm Technologies, Inc. in Raleigh, NC.  He directs the research and development of circuit and system technologies to improve the performance, energy efficiency, yield, reliability, and security of Qualcomm processors.  Dr. Bowman and his team pioneered four commercially successful circuit and system solutions, significantly benefiting CPUs, GPUs, neural processing units (NPUs), and secure processing unit (SPUs) across internet-of-things (IoT), mobile, laptop, and automotive platforms.  He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering.  His career includes a 12-year tenure at Intel Corporation in Hillsboro, OR prior to joining Qualcomm in 2013.

Dr. Bowman has published over 90 technical papers, received more than 100 patents, and given over 50 tutorial, special-session, and keynote presentations.  His contributions have been recognized with the 2016 Qualcomm Corporate Research and Development (CRD) Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, and the 2022 Qualcomm IP Achievement Award.  He has held various leadership roles within the IEEE Solid-State Circuits Society (SSCS) such as serving as an IEEE SSCS Distinguished Lecturer, IEEE SSCS Mentor, and multiple technical committee positions for the IEEE International Solid-State Circuits Conference (ISSCC).  He currently serves as the ISSCC 2026 Program Chair.  He is a Fellow of the IEEE.

The webinar is free, but registration is required. The Zoom session link will be sent after registration. 

Register Here

ACRC Event: Celebrating 25 Years of the Flash Drive: A Conversation with Its Inventor, Dov Moran

The Technion invites students, faculty, and industry partners to a special conversation with Dov Moran, entrepreneur, inventor of the USB flash drive, Technion alumnus, and recipient of an honorary doctorate.

In this talk, moderated by Prof. Shahar Kvatinsky, Moran will share the story behind the development and global impact of the flash drive, the challenges of bringing a revolutionary hardware product to market, and his perspective on the future of hardware innovation. He will also discuss the unique strengths Technion graduates bring to today’s high-tech ecosystem.

Dov Moran is one of Israel’s most influential figures in global technology—an entrepreneur, venture capitalist, and founder of Grove Ventures, a leading VC fund managing roughly half a billion dollars.

The event will take place on Wednesday, November 26, 2025, at 12:30, in Auditorium 1003, 10th floor, Meyer Building.

Registration: https://forms.office.com/r/sLY0fYd2Xz

ACRC Webinar: Secure In-memory Computing Architectures

Date: November 19, 2025 – Wednesday

Time: 17:00 – 18:30 Israel Time

Speaker: Dr. Farhad Merchant, Bernoulli Institute – the University of Groningen, the Netherlands

Language: English

Register Here

Abstract: 

In this talk, I will introduce my research group’s activities, outlining our general philosophy and key research directions. I will begin with MAGIC-based in-memory computing (IMC) architectures, detailing their experimental validation—with emphasis on MAGIC OR and NOT implementations. Expanding beyond general-purpose IMC, I will present our work on application-specific implementations of the Tsetlin machine, demonstrating its tailored efficiency for targeted workloads. The discussion will then shift to our hardware prototyping efforts, bridging theory and practice. Finally, I will highlight advances in hardware-oriented security and trust, including physically unclonable functions (PUFs), true random number generators (TRNGs), and integrated security architectures—addressing critical challenges in modern computing systems.

Bio:

Farhad is trained in electronics engineering and received his PhD from the Indian Institute of Science, Bangalore. After his PhD, he worked in industry (Bosch Research) and academia (NTU and RWTH Aachen University), in various research roles such as researcher and postdoctoral research fellow. Farhad worked at Newcastle University as a Lecturer (Assistant Professor) from December 2022 until June 2024. He joined the University of Groningen as an Assistant Professor of Innovative Computer Architecture at the Bernoulli Institute on July 1, 2024. He is also affiliated to CogniGron.

His research interests are emerging technology-based computing and hardware-oriented security. Farhad has received the best paper awards at ISQED 2022, NEWCAS 2023, and VLSI-DAT 2024. Besides, he has received a Minerva Short-Term fellowship to visit Technion – Israel Institute of Technology, the HiPEAC technology transfer award in 2019, and the DAAD Sandwich Model scholarship during his PhD to visit RWTH Aachen University, Germany. Farhad also serves as a technical programme committee member in major conferences such as DAC, ISLPED, ICCAD, ESWeek, ICCD, and VLSI-SoC. He is an associate editor in the IEEE Embedded System Letters. He has co-founded an annual workshop entitled Secure Hardware, Architectures, and Software – SeHAS, which has been organised at the HiPEAC conference since 2019. Farhad is the coordinator of the REACT Doctoral Network funded by MSCA (project-react.eu)

The webinar is free, but registration is required. The Zoom link will be sent after registration. 

Register Here