Date: July 28, 2025, Monday

Time: 16:00 – 17:30 Israel Time

Speaker: Ricardo Reis, Instituto de Informática, Universidade Federal do Rio Grande do Sul, at Porto Alegre, Brazil

Language: English

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Abstract:

A way to reduce power consumption is to reduce the number of transistors used to implement a circuit, as leakage power is proportional to the number of transistors. It is shown a physical design approach to reduce the number of transistors needed to perform a task. It is proposed an EDA tool set to automatically generate the physical design of any transistor network. It shows an important reduction on power, improving also reliability. A standard cell library has a limited number of logical functions, and a limited number of sizings. The talk is target in optimization methods to reduce the number of transistors of a circuit. The methods allow the realization of any possible logical function or transistor network. It is included comparisons with solutions using the traditional standard cell methodology.

Speaker Bio: 

Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 750 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, 2018 and 2022, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. He is the CASS representative at the IEEE IoT Technical Committee. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022. He received the 2023 IEEE CASS John Choma Educational Award and the 2024 Best Associate Editor of IEEE CASS Magazine. He is also Distinguished Lecturer of IEEE CEDA (2024-2025).

The webinar is free, but registration is required. Zoom link will be sent after registration. 

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Date: June 29, 2025, Sunday

Time: 16:00 – 17:30 Israel Time

Speaker: Victor Grimblatt, Synopsys

Language: English

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Abstract: 

In an era where sustainability is essential, designing low-power integrated circuits (ICs) plays a crucial role in reducing energy consumption and mitigating environmental impact. This talk examines innovative strategies in low-power IC design to meet the increasing demand for energy-efficient electronics, from IoT devices to large-scale computing systems. By utilizing advanced techniques such as subthreshold operation, power gating, clock gating, and dynamic voltage scaling, we outline a framework for optimizing performance while minimizing power dissipation. The discussion emphasizes the interplay between circuit-level innovations, such as the strategic use of clock gating to reduce dynamic power in idle states, process technology advancements, and system-level integration, highlighting their collective contribution to sustainability. Through simulations and case studies, we demonstrate how these approaches can significantly lower the carbon footprint of electronic systems, paving the way for greener technology solutions that align with global sustainability goals.

Title: On Entrepreneurship, Academia, and Deep Learning

Date: June 04, 2025, Wednesday

Time: 12:30 – 14:30

Location: 1003, Mayer Building, Technion

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Abstract: 

This talk will begin by describing a few foundational elements of deep learning along with elementary concepts in neural network inference optimization to provide context for understanding the work and innovations at Deci AI, a neural network design and optimization startup that was acquired by NVIDIA in 2024. Following this light technical discussion, we’ll tell the story of building Deci, sharing practical lessons from the startup journey including both successes and challenges encountered along the way, and touch on the relationship between academic research and entrepreneurship in the AI field.

Speaker Bio:

Ran El-Yaniv is a Professor of Computer Science at the Technion (currently on leave) and Senior Director at NVIDIA where he leads the Deci research team following NVIDIA’s 2024 acquisition
of Deci AI, which he co-founded. The Deci team at NVIDIA focuses on building efficient large language models and contributed significantly to the design and creation of one of the currently leading open-source LLMs, recently released, working alongside other teams at NVIDIA. El-Yaniv holds a PhD in Computer Science from the University of Toronto and completed postdoctoral work at MIT and the Hebrew University. His academic research focuses on selective prediction and uncertainty estimation, computational creativity, financial modeling, and AI including large language models. He coauthored the textbook “Online Computation and Competitive Analysis” (Cambridge University Press) and received the 2016 Yanai Prize for Excellence in Academic Education at the Technion.

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Title: Composable Chiplets

Date: 15th May, 2025

Time: 11:00 – 12:00 Israel Time

Location: 506 Zisapel Building, Technion and Zoom

Language: English

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Abstract:

Chiplets present a compelling approach to reducing the cost and time of chip design by raising the abstraction level to the die. In this talk, I will share my decade-long experience with chiplets and examine the current challenges blocking effective chiplet-based design for startups, government, and academia. Additionally, I will introduce recent work on composable (“interchangable”) chiplets, where O(M^N) unique silicon systems can be assembled from N chiplets arbitrarily selected from a library of size M. To illustrate the potential of this approach, consider a 10 chiplet system built from a library of 10 chiplets, enabling the creation of 10⁹ unique configurations. In contrast, fewer than 10³ unique chip tapeouts occur worldwide each year.  Standing up a practical composable chiplet platform on par with the existing SoC design ecosystem will require enormous investments, but if done right has the potential of fundamentally disrupting the semiconductor industry.

Biography:

Andreas Olofsson is the founder and CEO of Zero ASIC, a semiconductor startup on a mission to democratize silicon. From 2017 – 2020, Andreas was a program manager at DARPA, where he managed 8 different US research programs in heterogeneous integration, EDA, high performance computing, machine learning, and analog computing. From 2008-2017, Andreas founded and managed Adapteva, an ultra lean fabless semiconductor startup that led the industry in processing energy efficiency. Prior to Adapteva he worked at Analog Devices for 10 years as a design manager and architect for advanced DSPs and mixed signal devices, developing products that shipped in over 100 million systems. Andreas received his Bachelor of Science in Physics and Electrical Engineering and Master of Science in Electrical Engineering from the University of Pennsylvania. He is a senior member of IEEE and holds nine U.S. patents.

Date: 18th May, 2025

Time: 18:00 – 19:30 Israel Time

Language: English

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Abstract:

Security in IoT sensors has focused on cryptography-based but has failed to consider System-on-Chip (SoC) interoperability during side-channel, and physical attacks, as they concentrate solely on standalone behavior. This talk will discuss SoC security solutions that shield a SoC against supply voltage and physical attacks while apprising SoC interoperation. Along with the supply monitoring shields, this talk will present an efficient AES-256b encryption module accelerator, a physical unclonable function, and a true random number generator as SoC peripheral instances.

Bio:
Elkim received his Ph.D. degree in Electrical and Computer Engineering from Purdue University in 2014, where he was a Fulbright Scholar, his M.S degree from the University of São Paulo, São Paulo, Brazil, and his bachelor’s degree in Electrical Engineering from Universidad Industrial de Santander, Colombia. He is currently a SoC Architect in Samsung Semiconductor Inc. working on computing acceleration for 4G/5G modems systems. Prior to Samsung, he has worked with Rambus Inc. and GlobalFoundries on high-speed communications, systems engineering for projects solving communications bandwidth and computing bottlenecks. He was an Associate Professor at Universidad Industrial de Santander from 2016 to 2021. His research interests include SoC architecture, high-speed interfaces, computing acceleration, and efficient AI computing.

The webinar is free but registration is required. Zoom link will be sent after registration. 

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Date: 07th April, 2025

Time: 16:00 – 17:30 Israel Time

Language: English

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Abstract:

Chiplet-based design is emerging as a key strategy to address the limitations of traditional monolithic semiconductor design, especially as Moore’s Law approaches its physical limits. By partitioning complex systems into smaller, manageable “chiplets,” designers can achieve improved scalability, flexibility, and cost efficiency. Chiplet architecture allows different components of a system-on-chip (SoC) to be developed, manufactured, and integrated separately, facilitating the use of mixed-process technologies, modular upgrades, and faster time-to-market.Despite its potential, chiplet design presents several challenges. This overview explores an overview of chiplet design ranging from die to die interface, interoperability, packaging, cost , design process, signoff check, chiplet builder, thermal performance, repairability and challenges. Hopefully, it will prepare the designer in advance from design planning phase.

Bio:

Ang Boon Chong was born in Penang, Malaysia, in 1978. He received the B.E. degree in microelectronic engineering from the University Putra Malaysia, Malaysia, in 2002, and MBA from Open University Malaysia, Malaysia in 2014. He is currently affiliated with Intel Malaysia, been engaged in a wide variety of advanced nodes and methodology evaluation. He has published over 50 papers, books, white papers as well as delivered invited talks in various workshop and IEEE conferences. He is currently a tech lead within the organization as well as IEEE senior member.

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Date: 24th March, 2025

Time: 16:00 – 17:30 Israel Time

Language: English

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Abstract:

To overcome the ever-increasing design challenges of radio front end for wireless communications, extensive research efforts have been devoted to advance the RF transmitters in recent years at both industry and academia. This talk provides an introduction on the innovations leading to more advanced digital and intelligent RF transmitters. First, an overview and the technical challenges on designing and implementation of All-digital transmitter will be introduced covering both hardware and software aspects, including active devices, switching-mode PA operation, efficient and spurious-free power encoding of signals. Then advanced techniques with demonstrators of All-digital transmitter and All-digital phased array will be showcased. In addition, Machine learning and AI techniques applied to enhance the agility and performance (i.e. operating bandwidth, efficiency, linearity) of (digital) radio transmitter will be highlighted. Perspectives on the future directions of radio transmitter towards a greener and smarter wireless communication will be shared at the end.

Biography:

Rui Ma received his Dr.-Ing. degree in Electrical Engineering from the University of Kassel, Kassel, Germany, in 2009. From 2007-to 2010, he was with the Microwave Electronics Labs at the University of Kassel as a Research Scientist working on transistor modeling and RF power amplifier design. From 2010-to 2012, he was a Senior Research Engineer with Nokia Siemens Networks, where he focused on the R&D of enabling power amplifier technologies for wideband radio at NSN Research Center in Beijing, China. From 2012 to 2022, he was with Mitsubishi Electric Research Laboratories in Cambridge, USA, where he was a Senior Principal Scientist of RF Research, responsible for technologies focused on power amplifiers, digital transmitters, 5G radio, as well as emerging applications of GaN. In 2013, he received the specification award by MIPI Alliance for the development of Analog Reference Interface (ACI) for Envelope Tracking eTrak specification. In 2019, he was awarded Mitsubishi Electric President Award for his contributions to GaN development and its RF applications. In July 2022, Dr. Ma joined pSemi, A Murata Company, where he is currently a Director of mmWave PA Systems. Dr. Ma is a senior member of IEEE and inventor or co-inventor for more than 25 U.S. patents and patent applications on RF-related topics. He serves MTT-S AdCom Committee since 2016. He is MTT Boston Chapter Chair since April 2018. Dr. Ma has also been a Visiting Scientist with THz Integrated Electronics Group at the Massachusetts Institute of Technology (MIT) from 2016 to 2021. He is an Associate Editor of IEEE Transactions on Microwave Theory and Techniques, and Associate Editor of IEEE Journal of Electromagnetics, RF and Microwaves in Medicine and Biology.

The webinar is free but registration is required. Zoom link will be sent after registration. 

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Date: 27th January, 2025

Time: 17:00 – 18:30 Israel Time

Language: English

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Abstract:

DRAM standards have evolved tremendously over the last two-and-a-half decades, leading to diversification not only in the architecture of the memory array but also in that of the off-chip interface. Application-specific signaling channels have influenced the transceiver design nearly as much as system power and bandwidth requirements have. The influence of the multidrop server channel, along with a broad range of target environments, has led the DDR branch of JEDEC DRAMs to incorporate multi-tap Decision Feedback Equalization to maximize flexibility, while shrinking supply voltages to facilitate energy reduction have led Low-Power DDR (LPDDR) to completely rethink the output driver structure. In parallel, Graphics DDR (GDDR) has reached speeds requiring nearly equal care of the external channel and the chip itself. The adoption of multi-level signaling in GDDR6x and GDDR7 to relax on-chip frequency requirements has only heightened the need for more rigorous co-design of transceiver, package and system characteristics. And, of course, the integration of silicon interposers to support High Bandwidth Memory (HBM) has driven a paradigm shift in memory interface design. With all of these adaptations, and many others not captured here, the splintering DRAM family continues to push the boundaries of single-ended signaling into the future.

This presentation briefly explores what has driven the diversification in DRAM signaling schemes over the decades, will discuss the motivation behind present embodiments, and will project into the future to where the DRAM interface is likely headed (e.g., features and functions necessary for continued energy-efficient bandwidth scaling).

Bio: 

Tim Hollis received the Ph.D. degree in electrical engineering from Brigham Young University, Provo, UT, USA, in 2007.

In 2006, he joined the Advanced Architecture Group at Micron Technology in Boise, Idaho, USA where he contributed to several pathfinding activities including the first-generation Hybrid Memory Cube. From 2012 to 2014, he worked as a chipset architect at Qualcomm in San Diego, CA, USA. He returned to Micron in 2014, where he currently leads the Interface Pathfinding Group as a Micron Fellow. He has published 18 articles in journals, conference proceedings, and technical magazines, and holds 228 issued U.S. and international patents.

Dr. Hollis has been serving as a member of the IEEE Workshop on Microelectronics and Electron Devices Organizing Committee since 2010, including the General Chair in 2013. He has served on other IEEE conference committees as well as DesignCon’s Technical Program Committee from 2013 to 2015. From 2017 to 2020 he served as the Technology Editor for the IEEE Solid-State Circuits Magazine and as a Guest Editor for memory- and interface-related special issues in 2016 and 2019, respectively.

The webinar is free but registration is required. Zoom link will be sent after registration. 

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