Date: December 10, 2025, Wednesday

Time: 17:00 – 18:00 Israel Time

Speaker: Keith Bowman, Qualcomm Technologies

Language: English

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Abstract: 

As a follow up to the ACRC Webinar on Dec. 8th, this session provides an additional question and answer opportunity for attendees from university or industry to ask about a wide range of topics such as future technology directions, performing research in industry, transferring research ideas into products, etc.  Since some common questions from previous sessions relate to writing a Solid-State Circuits Society (SSCS) conference paper, this webinar covers this topic with a 20-minute presentation, covering the SSCS conference basics, the paper-rating criteria as presented at the IEEE International Solid-State Circuits Conference (ISSCC) Reviewer Training, and the key steps for organizing and writing a strong SSCS conference submission.

Biography:

Keith A. Bowman is a Principal Engineer and Director of the System-on-Chip Research Lab at Qualcomm Technologies, Inc. in Raleigh, NC.  He directs the research and development of circuit and system technologies to improve the performance, energy efficiency, yield, reliability, and security of Qualcomm processors.  Dr. Bowman and his team pioneered four commercially successful circuit and system solutions, significantly benefiting CPUs, GPUs, neural processing units (NPUs), and secure processing unit (SPUs) across internet-of-things (IoT), mobile, laptop, and automotive platforms.  He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering.  His career includes a 12-year tenure at Intel Corporation in Hillsboro, OR prior to joining Qualcomm in 2013.

Dr. Bowman has published over 90 technical papers, received more than 100 patents, and given over 50 tutorial, special-session, and keynote presentations.  His contributions have been recognized with the 2016 Qualcomm Corporate Research and Development (CRD) Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, and the 2022 Qualcomm IP Achievement Award.  He has held various leadership roles within the IEEE Solid-State Circuits Society (SSCS) such as serving as an IEEE SSCS Distinguished Lecturer, IEEE SSCS Mentor, and multiple technical committee positions for the IEEE International Solid-State Circuits Conference (ISSCC).  He currently serves as the ISSCC 2026 Program Chair.  He is a Fellow of the IEEE.

The webinar is free, but registration is required. The Zoom link will be sent after registration.

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Date: December 8, 2025, Monday

Time: 16:00 – 17:30 Israel Time

Speaker: Keith Bowman,  Qualcomm Technologies

Language: English

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Abstract: 

System-on-chip (SoC) processors across a wide range of market segments, including Internet of Things (IoT), mobile, laptop, automotive, and datacenter, experience dynamic device, circuit, and system parameter variations during the operational lifetime.  These dynamic parameter variations, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations, degrade processor performance, energy efficiency, yield, and reliability.  This webinar introduces the primary variation sources and the negative impact of these variations across voltage and clock frequency operating conditions.  Then, this webinar presents adaptive processor designs to mitigate the adverse effects from dynamic parameter variations while highlighting the key trade-offs and considerations for product deployment.

Biography:

Keith A. Bowman is a Principal Engineer and Director of the System-on-Chip Research Lab at Qualcomm Technologies, Inc. in Raleigh, NC.  He directs the research and development of circuit and system technologies to improve the performance, energy efficiency, yield, reliability, and security of Qualcomm processors.  Dr. Bowman and his team pioneered four commercially successful circuit and system solutions, significantly benefiting CPUs, GPUs, neural processing units (NPUs), and secure processing unit (SPUs) across internet-of-things (IoT), mobile, laptop, and automotive platforms.  He received the B.S. degree from North Carolina State University in 1994 and the M.S. and Ph.D. degrees from the Georgia Institute of Technology in 1995 and 2001, respectively, all in electrical engineering.  His career includes a 12-year tenure at Intel Corporation in Hillsboro, OR prior to joining Qualcomm in 2013.

Dr. Bowman has published over 90 technical papers, received more than 100 patents, and given over 50 tutorial, special-session, and keynote presentations.  His contributions have been recognized with the 2016 Qualcomm Corporate Research and Development (CRD) Distinguished Contributor Award for Technical Contributions, representing CRD’s highest recognition, and the 2022 Qualcomm IP Achievement Award.  He has held various leadership roles within the IEEE Solid-State Circuits Society (SSCS) such as serving as an IEEE SSCS Distinguished Lecturer, IEEE SSCS Mentor, and multiple technical committee positions for the IEEE International Solid-State Circuits Conference (ISSCC).  He currently serves as the ISSCC 2026 Program Chair.  He is a Fellow of the IEEE.

The webinar is free, but registration is required. The Zoom session link will be sent after registration. 

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Date: November 19, 2025 – Wednesday

Time: 17:00 – 18:30 Israel Time

Speaker: Dr. Farhad Merchant, Bernoulli Institute – the University of Groningen, the Netherlands

Language: English

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Abstract: 

In this talk, I will introduce my research group’s activities, outlining our general philosophy and key research directions. I will begin with MAGIC-based in-memory computing (IMC) architectures, detailing their experimental validation—with emphasis on MAGIC OR and NOT implementations. Expanding beyond general-purpose IMC, I will present our work on application-specific implementations of the Tsetlin machine, demonstrating its tailored efficiency for targeted workloads. The discussion will then shift to our hardware prototyping efforts, bridging theory and practice. Finally, I will highlight advances in hardware-oriented security and trust, including physically unclonable functions (PUFs), true random number generators (TRNGs), and integrated security architectures—addressing critical challenges in modern computing systems.

Bio:

Farhad is trained in electronics engineering and received his PhD from the Indian Institute of Science, Bangalore. After his PhD, he worked in industry (Bosch Research) and academia (NTU and RWTH Aachen University), in various research roles such as researcher and postdoctoral research fellow. Farhad worked at Newcastle University as a Lecturer (Assistant Professor) from December 2022 until June 2024. He joined the University of Groningen as an Assistant Professor of Innovative Computer Architecture at the Bernoulli Institute on July 1, 2024. He is also affiliated to CogniGron.

His research interests are emerging technology-based computing and hardware-oriented security. Farhad has received the best paper awards at ISQED 2022, NEWCAS 2023, and VLSI-DAT 2024. Besides, he has received a Minerva Short-Term fellowship to visit Technion – Israel Institute of Technology, the HiPEAC technology transfer award in 2019, and the DAAD Sandwich Model scholarship during his PhD to visit RWTH Aachen University, Germany. Farhad also serves as a technical programme committee member in major conferences such as DAC, ISLPED, ICCAD, ESWeek, ICCD, and VLSI-SoC. He is an associate editor in the IEEE Embedded System Letters. He has co-founded an annual workshop entitled Secure Hardware, Architectures, and Software – SeHAS, which has been organised at the HiPEAC conference since 2019. Farhad is the coordinator of the REACT Doctoral Network funded by MSCA (project-react.eu)

The webinar is free, but registration is required. The Zoom link will be sent after registration. 

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Speaker: Prof. Ilia Polian, University of Stuttgart

Date: November 10th, 2025, Monday

Time: 13:30 – 14:30 Israel Time

Location: Room 608 Zisapel Building (New), Technion

Language: English

Abstract: 

Memristive technologies offer fascinating opportunities for unconventional computing architectures and emerging applications. With their combined compute and storage capability, memristive devices enable in-memory architectures that overcome the von-Neumann bottleneck, neuromorphic computing, and a range of security application. Memristive circuits are particularly attractive for cryptographic computations, where secret keys can be stored in the devices without any external memory interfacing, and stateful computations facilitate secure use of nonces (numbers used once).
This talk, based on a longstanding collaboration between the presenter and Dr. Nan Du of Leibnitz IPHT Jena, will focus on the novel mixed-mode (MM) memristive computing, where the same device performs a mixture stateful resistance-controlled and non-stateful voltage-control operations. It will discuss automated synthesis of MM synthesis, showing an optimal approach for small functions based on Boolean satisfiability and a more scalable procedure that utilizes majority-inverter graphs. The MM paradigm leads to 3-5 times more compact realizations of user-defined functions than conventional memristive computing.
A second focus of the talk will be on the vulnerability of memristive cryptographic circuits to physical attacks. We explore in-depth the side-channel analysis through the power channel and show the new mPEM (memristive power estimation model) that is effective in attacking unprotected memristive circuits, both in simulation and using actual measured data of small fabricated circuits based on experimental BiFeO3 devices. We show that the advantages of memristive devices, such as their nonvolatility and the memory effect, can dialectically become their disadvantages and lead to new side-channels that did not exist in conventional CMOS technology. Based on these observations, we discuss countermeasures against side-channel attacks: hiding based on power equalization, and masking based on randomized computations. We study conditions under which solutions known from CMOS continue to be effective in the memristive domain and where new approaches are necessary.

Bio: 

Ilia Polian is a Full Professor and the Director of the Institute for Computer Architecture and Computer Engineering at the University of Stuttgart, Germany. He received his Diplom (MSc) and PhD degrees from the University of Freiburg, Germany, in 1999 and 2003, respectively. Prof. Polian co-authored over 250 scientific publications and received two Best Paper Awards. He is a Senior Mem­ber of IEEE. Prof. Polian is the Speaker of DFG’s Priority Program 2253 “Nano Security”, a Director of the Graduate School “Intelligent Methods for Test and Reliability” in Stuttgart (funded by Advantest) and of the Center for Integrated Quantum Science and Technology (IQST). His scientific interests include hardware-oriented security, emerging architectures, test methods, and quantum computing.

Date: October 29, 2025

Time: 16:00 – 17:30 Israel Time

Speaker: Prof. Rabia Tugce Yazicigil, Boston University

Language: English

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Abstract: 

This talk will introduce Cyber-Secure Biological Systems, leveraging living sensors constructed from engineered biological entities seamlessly integrated with solid-state circuits. This unique synergy harnesses the advantages of biology while incorporating the reliability and communication infrastructure of electronics, offering a unique solution to societal challenges in healthcare and environmental monitoring. In this talk, examples of Cyber-Secure Biological Systems, such as miniaturized ingestible bioelectronic capsules for gastrointestinal tract monitoring and hybrid microfluidic-bioelectronic systems for environmental monitoring, will be presented.

Additionally, I will introduce a universal noise-centric data decoding approach using GRAND that facilitates ultra-low-energy wireless communications, a critical requirement for the success of these biological systems and numerous other applications. In this talk, I will delve into the intricacies of interdisciplinary approach for system design, spotlighting the potential of energy-efficient integrated circuits in the domains of biosensing and wireless communications. These collaborative research projects involve MIT BE/MechE, BU ECE/BME, and MIT RLE-Northeastern University.

Biography:

Rabia Tugce Yazicigil is an Associate Professor of ECE Department at Boston University and a Network Faculty at Sabanci University. She was a Postdoctoral Associate at MIT and received her Ph.D. degree from Columbia University in 2016. Her research interests lie at the interface of integrated circuits, bio-sensing, signal processing, security, and wireless communications to innovate system-level solutions for future energy constrained applications. She has received numerous awards, including the NSF CAREER Award (2024), Early Career Excellence in Research Award for the Boston University College of Engineering (2024), the Catalyst Foundation Award (2021), Boston University ENG Dean Catalyst Award (2021), and “Electrical Engineering Collaborative Research Award” for her Ph.D. research (2016). Dr. Yazicigil is an active member of the Solid-State Circuits Society (SSCS) Women-in-Circuits committee and is a member of the 2015 MIT EECS Rising Stars cohort. She was selected as an IEEE SSCS and CASS Distinguished Lecturer for the 2024-2026 term and elected to the IEEE SSCS AdCom as a Member-at-Large in 2024. She was selected as a member of the 2024 National Academy of Engineering (NAE) US Frontiers of Engineering (USFOE) cohort. She serves as an Associate Editor of the IEEE Transactions on Circuits and Systems-I (TCAS-I) and the IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI). Additionally, she is the Workshop Co-Chair of the IEEE ESSERC 2024, and a Technical Program Committee member of the IEEE ISSCC and RFIC.

The webinar is free, but registration is required. The Zoom link will be sent after registration. 

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Date: July 28, 2025, Monday

Time: 16:00 – 17:30 Israel Time

Speaker: Ricardo Reis, Instituto de Informática, Universidade Federal do Rio Grande do Sul, at Porto Alegre, Brazil

Language: English

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Abstract:

A way to reduce power consumption is to reduce the number of transistors used to implement a circuit, as leakage power is proportional to the number of transistors. It is shown a physical design approach to reduce the number of transistors needed to perform a task. It is proposed an EDA tool set to automatically generate the physical design of any transistor network. It shows an important reduction on power, improving also reliability. A standard cell library has a limited number of logical functions, and a limited number of sizings. The talk is target in optimization methods to reduce the number of transistors of a circuit. The methods allow the realization of any possible logical function or transistor network. It is included comparisons with solutions using the traditional standard cell methodology.

Speaker Bio: 

Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 750 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, 2018 and 2022, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. He is the CASS representative at the IEEE IoT Technical Committee. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022. He received the 2023 IEEE CASS John Choma Educational Award and the 2024 Best Associate Editor of IEEE CASS Magazine. He is also Distinguished Lecturer of IEEE CEDA (2024-2025).

The webinar is free, but registration is required. Zoom link will be sent after registration. 

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Date: June 29, 2025, Sunday

Time: 16:00 – 17:30 Israel Time

Speaker: Victor Grimblatt, Synopsys

Language: English

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Abstract: 

In an era where sustainability is essential, designing low-power integrated circuits (ICs) plays a crucial role in reducing energy consumption and mitigating environmental impact. This talk examines innovative strategies in low-power IC design to meet the increasing demand for energy-efficient electronics, from IoT devices to large-scale computing systems. By utilizing advanced techniques such as subthreshold operation, power gating, clock gating, and dynamic voltage scaling, we outline a framework for optimizing performance while minimizing power dissipation. The discussion emphasizes the interplay between circuit-level innovations, such as the strategic use of clock gating to reduce dynamic power in idle states, process technology advancements, and system-level integration, highlighting their collective contribution to sustainability. Through simulations and case studies, we demonstrate how these approaches can significantly lower the carbon footprint of electronic systems, paving the way for greener technology solutions that align with global sustainability goals.