“Embedded Systems Design in the Era of AI” by Prof. Michael Huebner

The increasing demands of complexity, flexibility and self-organization of networked embedded systems require new solutions for the local processor architectures and firmware. This includes the ability to adapt to the requirements of an algorithm e.g. in relation to a sensor value measured by an Cyberphysical System. Artificial intelligence becomes ubiquitous and therefore enters also the domain of embedded systems and enables enormous opportunities in edge computing. This will introduce new degrees of freedom in embedded and Cyberpyhsical systems and is very promising to support the aforementioned demands tremendously. In this talk, possible solutions for next generation embedded systems with AI components will be introduced.

Michael Huebner is a Full Professor and leads the Chair for Computer Engineering at the Brandenburg University of Technology (BTU) in Cottbus, Germany, since 2018.

He is also Vice-President for research and transfer at BTU since December 2020.

He received his diploma degree in electrical engineering and information technology in 2003, his Ph.D. degree in 2007 from the University of Karlsruhe (TH), and did his habilitation in 2011 at the Karlsruhe Institute of Technology (KIT) in the domain of reconfigurable computing systems.

His research interests are in reconfigurable computing and particularly new technologies for adaptive FPGA run-time reconfiguration and on-chip network structures with application in automotive systems, incl. the integration into high-level design and programming environments.

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“An Organic-Photoconductive-Film CMOS Image Sensor’s Advanced Technologies” by Kazuko Nashimura

We have developed a CMOS image sensor with an organic photoconductive film (OPF) laminated on pixel circuits, different from those of a conventional silicon image sensors, in which the organic thin film for photoelectric conversion and the charge storage part for signal charge accumulation are completely independent. In this presentation, we focus on the advantageous features of the OPF image sensor; [1] technology that realizes over 120 dB simultaneous-capture wide dynamic range; [2] global shutter technology achieving high saturation signals per unit square that is 10 dB higher than that of silicon image sensors with the global shutter function, without sacrificing pixel area; [3] RGB-NIR sensor technology capable of controlling NIR sensitivity by simply controlling the voltage applied to the OPF. Moreover, we introduce about 8K4K high resolution sensor technologies with 60fps high frame rate, 450ke- high saturation signals, and the global shutter function at the same time. We believe these features of the OPF image sensor will contribute to leaps in the imaging and sensing fields.

Kazuko Nishimura received the B.E. degree in mechanical engineering from Osaka University, and joined Panasonic Corporation where she engaged in high-speed analog-to-digital converters (ADCs) in 1995. She developed optical communication systems for fiber-to-the-home (FTTH), RF tuners and CMOS image sensors. Currently, she is a manager in Technology Division (R&D Division), Panasonic Corporation and pursues research on the organic photoconductive film (OPF) CMOS image sensors and sensor applications. She serves A-SSCC data converter subcommittee chair and ISSCC Imagers, Medical, MEMS and Displays subcommittee, IEEE SSCS distinguished Lecturer, and the SSCS Adcom. She is a senior member of IEEE.

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“Hardware Security and Safety of IC Chips” webinar by Prof. Makoto Nagata

IC chips are key enablers to a smartly networked society and need to be more compliant to security and safety. For example, semiconductor solutions for autonomous vehicles must meet stringent regulations and requirements. While designers develop circuits and systems to meet the performance and functionality of such products, countermeasures are proactively implemented in silicon to protect against harmful disturbances and even intentional adversarial attacks.

This talk will start with Electromagnetic Compatibility (EMC) techniques applied to IC chips for safety to motivate EMC-aware design, analysis, and implementation. It will discuss IC design challenges to achieve higher levels of hardware security (HWS). Crypto-based secure IC chips are investigated to avoid the risks of side-channel leakages and side-channel attacks, corroborated with silicon demonstrating analog techniques to protect digital functionality. The EMC and HWS disciplines derived from electromagnetic principles are key to establishing IC design principles for security and safety.

Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, in 1991 and 1993, respectively, and a Ph.D. in electronics engineering from Hiroshima University, Hiroshima, in 2001.. He is currently a professor of the graduate school of science, technology and innovation, Kobe University, Kobe, Japan. He is a senior member of IEICE and IEEE.

His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety.

Dr. Nagata has been a member of a variety of technical program committees of international conferences. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-present). He is also serving as SSCS AdCom member since 2020. He is currently an associate editor for IEEE Transactions on VLSI Systems (2015-present).

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“Asynchronous Stream Computing for Low Power IoT – Asynchronous Stochastic Computing (ASC), Asynchronous Stream Processing (ASP) and Asynchronous Impulse Radio (AIR) for ubiquitous sensing at the Edge” webinar by Prof. Mircea R. Stan

Asynchronous circuits have many potential advantages over their synchronous counterparts in terms of robustness to parameter variations, wide supply voltage ranges, and potentially low power by not needing a clock, yet their promise has not been translated yet into commercial success due to several issues related to design methodologies and the need for handshake signals. Stochastic computing is another processing paradigm that has shown promises of low power and extremely compact circuits but has yet to become a commercial success mainly because of the need for a fast clock to generate the random streams.
In this talk we will go over three complementary circuit techniques: Asynchronous Stochastic Computing (ASC), Asynchronous Stream Processing (ASP) and Asynchronous Impulse Radio (AIR). These techniques combine the best features of asynchronous circuits with the best features of stochastic computing to enable extremely compact and low power IoT sensing nodes. Together they can fulfill the promise of smart dust, a concept that was ahead of its time and yet to achieve commercial success.

Mircea R. Stan is the Virginia Microelectronics Consortium (VMEC) professor at the University of Virginia. He is teaching and doing research in the areas of high-performance low-power VLSI, Processing in Memory, temperature-aware circuits and architecture, Cyber-Physical Systems, spintronics, and nanoelectronics. He leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). He received the 2018 Influential ISCA Paper Award, the NSF CAREER award in 1997 and was a co-author on best paper awards at ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. Prof. Stan is a fellow of the IEEE, a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.

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“Closed-Loop Neuromodulation”

Facing a growing number of patients with neurological disorders, there are only limited therapeutic pharmacological measures which provide only temporary and mild amelioration of the devastating symptoms of these disorders. The use of electrical stimulation of the brain is a treatment option for patients with severe treatment-resistant disorders. Current deep-brain stimulation (DBS) approaches are hindered by inadequate technology that is low-precision and bulky, power-inefficient, and of limited diagnostic utility. The seminar will discuss a high-precision implantable neurotechnology for closed-loop neuromodulation of functional networks of the human brain. Key features of the technology are: 1) sensing from a high number of channels, 2) sensing concurrent with stimulation for true closed-loop operation, and 3) real-time secure wireless data telemetry. The proposed neurotechnology could revolutionize brain therapies in efficacy, size and cost of medical implants.

Dejan Marković is a Professor of Electrical and Computer Engineering at the University of California, Los Angeles (UCLA). He is also affiliated with UCLA Bioengineering Department, Neuroengineering field. He completed the Ph.D. degree in 2006 at the University of California, Berkeley, for which he was awarded 2007 David J. Sakrison Memorial Prize. His current research is focused on implantable neuromodulation systems, domain-specific compute architectures, and design methodologies. Dr. Marković co-founded Flex Logix Technologies, a semiconductor IP startup, in 2014, and helped build foundational technology of Ceribell, a medical device startup. He received an NSF CAREER Award in 2009. In 2010, he was a co-recipient of ISSCC Jack Raper Award for Outstanding Technology Directions. He also received 2014 ISSCC Lewis Winner Award for Outstanding Paper. Prof. Markovic is an IEEE Fellow.

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“Circuits and architectures with ultra-wide power-performance adaptation – going way beyond voltage scaling”

Wide power-performance adaptation down to nWs has become crucial in always-on nearly real-time and energy-autonomous SoCs that are subject to wide variability in the power availability and the performance target. Wide adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of SoCs having an extremely wide performance-power scalability and adaptation, so that they can relentlessly operate without interruption in spite of the highly-uncertain power availability.

In this talk, new directions to drastically extend the performance-power scalability of digital, analog and power management circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path in the digital sub-system. New directions to achieve full-system coordinated power-performance scaling are also discussed. Silicon demonstrations and trends in the state of the art of battery-light, battery-less and battery-indifferent SoCs are illustrated to quantify the benefits offered by wide power-performance adaptation, identifying opportunities and challenges for the decade ahead. Finally, an always-on mm-scale integrated system that operates uninterruptedly when solely powered by moonlight is demonstrated, paving the way to a new generation of always-on systems with little to no battery.

Massimo Alioto is a Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, and is the Director of the Integrated Circuits and Embedded Systems area and the FD-FAbrICS research center on intelligent&connected systems. He held positions at the University of Siena, Intel Labs CRL, University of Michigan Ann Arbor, University of California Berkeley, EPFL – Lausanne.

He is (co)author of 300 publications on journals and conference proceedings, and four books with Springer. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies.

He is the Editor in Chief of the IEEE Transactions on VLSI Systems, Distinguished Lecturer for the IEEE Solid-State Circuits Society, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012), as well as Distinguished Lecturer (2009-2010) and member of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2023, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.

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“A Flexible vision for RF ICs” by Dr. Matan Gal-Katziri

Flexible high-speed systems and architectures have promising and exciting applications at the intersection of communications, imaging, medicine and deployable arrays. The flexibility is expressed in terms of electrical reconfigurability, flexible circuit board materials, and lightweight, bendy interconnects between remote array elements. In this talk I will present my work at Caltech’s High-speed and holistic IC laboratory in developing such systems. Two key elements in our flexible schemes are the utilization of highly functional RFICs to minimize rigid component count, and a holistic, modular design approach which is crucial to future size scaling. Through the talk I will present several exemplary architectures for space, power transfer, communication and sensing applications, and will discuss the high-level considerations, implementation, challenges, and potential uses of such systems.

Matan Gal-Katziri received the B.S. degrees in Physics and Electrical Engineering from Ben-Gurion University, Beer-Sheva, Israel in 2009, and M.S. and Ph.D. degrees in electrical engineering from Caltech, Pasadena, CA, USA, in 2016 and 2020, respectively. He is currently a postdoctoral research associate in the department of electrical engineering at Caltech, Pasadena, CA. He is a part of Caltech’s Solar-Space Power Program RF design team, where his work on flexible arrays sheets has won the 2020 IMS advanced practice award. His research interests are high-frequency, integrated, and large-scale systems for medical, environmental, industrial and communications applications.

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“Human-Centric Computing” by Prof. Jan Rabaey

The world as we know it is going through some major upheavals: climate change, pandemics and technology-induced societal changes are upsetting our world-picture with no real end in sight. Hence, an extremely relevant question is how ‘we humans’ are going to cope with this rapid evolution. One plausible answer is for us to use those same technologies to evolve ourselves, and to equip us with the necessary tools to interact with, survive, and prosper in spite of (or in light of) these changes.

Various wearable devices have been or are being developed to do just that. However, their potential to create a whole new set of human experiences is still largely unexplored. To be effective, functionality cannot be centralized and needs to be distributed to capture the right information at the right place. This requires a human intranet, a platform that allows multiple distributed input/output and information processing functions to coalesce and form a single application. In this presentation, we focus on the computational aspects of such an intranet, tasks that are complicated by the extreme energy and form-factor limitations imposed on the wearable (or implanted) devices. An important aspect is that the human intranet should not only be able to learn from experience, but capable of dealing with changes in both the environment and in itself. Moreover, it should be able to do so on a continuous base. Computational models, architectures and circuits that enable such capabilities at ultra-low energy and small form factor are hence needed. A glimpse of what may be possible will be presented.

Jan Rabaey is a Professor in the Graduate School in the EECS Department at the University of California at Berkeley, where he held of the Donald O. Pederson Distinguished Professorship for over 30 years before retiring. Before joining the faculty at UC Berkeley, he was a research manager at IMEC from 1985 until 1987. He is a founding director of the Berkeley Wireless Research Center (BWRC) and the Berkeley Ubiquitous SwarmLab, and has served as the Electrical Engineering Division Chair at Berkeley twice. In 2019, he also became the CTO of the System-Technology Co-Optimization (STCO) Division of IMEC, Belgium.

Prof. Rabaey has made high-impact contributions to a number of fields, including advanced wireless systems, low power integrated circuits, mobile devices, sensor networks, and ubiquitous computing. His current focus is of the interaction between the cyber and the biological world (amongst many other things.

He is the recipient of major awards, amongst which the IEEE Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, the Semiconductor Industry Association (SIA) University Researcher Award, and the SRC Aristotle Award. He is an IEEE Fellow, a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has received a number of honorary doctorates. He has been involved in a broad variety of start-up ventures.

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“Sensor interfacing in the edge: small, sound, smart! ” by Prof. Gerald Gielen

The continuous progress of CMOS semiconductor technology fuels the technological revolution towards a smart world that immersivly impacts our daily life, work and play. The Internet of Things, personalized healthcare monitoring, autonomous driving, industry 4.0, etc. are but a few examples. Sensors and sensor interfaces with intelligence in the edge play a key role in all applications where the physical and the cyber worlds meet. This presentation will focus on core challenges in the design of future electronic circuits for such applications, where cost, power and reliability are major issues besides raw performance. The key to achieve solutions with small area (cost) and low power is to design the analog functions in a highly digital manner. Also ways to build intelligence in the edge will be discussed. This will be illustrated with some practical design examples.

Georges G.E. Gielen received the MSc and PhD degrees in EE from the KU Leuven, Belgium, in 1986 and 1990, respectively. He currently is Full Professor in the MICAS research division at the Department of Electrical Engineering (ESAT) at KU Leuven. From August 2013 till July 2017 he was also appointed at KU Leuven as Vice‐Rector for the Group of Sciences, Engineering and Technology, and he was also responsible for academic Human Resource Management.

He was visiting professor in UC Berkeley and Stanford University. Since 2020 he is Chair of the Department of EE.

His research interests are in the design of analog and mixed‐signal integrated circuits, and especially in analog and mixed‐signal CAD tools and design automation.

He is a frequently invited speaker/lecturer & coordinator/partner of several (industrial) research projects in this area, including several European projects. He has (co‐)authored 10 books and more than 600 papers in edited books, international journals and conference proceedings. He is a 1997 Laureate of the Belgian Royal Academy of Sciences, Literature and Arts in the discipline of Engineering. He is Fellow of the IEEE since 2002, and received the IEEE CAS Mac Van Valkenburg award in 2015 and the IEEE CAS Charles Desoer award in 2020. He is an elected member of the Academia Europaea.

Please sign up and join us on Tuesday, January 19, 2021 at 11:00 (Israel Standard Time).

A link to the Zoom session will be provided after registration.

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“Machine Learning and Optimization for Communications and Deep Networks”

In recent years, many remarkable achievements have been made in the field of machine learning. While most of the initial successes were related to image, speech and language recognition, a recent important development has been the application of these techniques to other areas. In particular, communications systems can benefit from applying these techniques. For example, algorithms such as Monte Carlo Markov Chain and Monte Carlo Tree Search have been successfully used in the design of MIMO (i.e., multiple antenna) transceivers. In addition, highly quantized implementations, such as binarized networks, have led to implementations that are well-suited to power-limited mobile platforms. In addition, metaheuristic optimization techniques such the genetic algorithm and others have been used to automatically find highly efficient deep learning architectures, eliminating the need for lengthy and tedious manual experimentation. This lecture will describe these approaches and present some recent design examples. Relationships between the algorithms will be emphasized, and important computational issues will be highlighted. Finally, opportunities for future research in these areas will be suggested.

Gerald Sobelman is a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, and he has served as the Director of Graduate Studies for the Graduate Program in Computer Engineering at the University of Minnesota. He received a B.S. degree in physics from the University of California, Los Angeles, and M.S. and Ph.D. degrees in physics from Harvard University. He has been a postdoctoral researcher at The Rockefeller University, and he has held senior engineering positions at Sperry Corporation and Control Data Corporation.

Prof. Sobelman is currently a Distinguished Lecturer of the IEEE Circuits and Systems Society. He has been a member of the technical program committees for several IEEE conferences. He was Chair of the Technical Committee on Circuits and Systems for Communications of the IEEE Circuits and Systems Society, and he has also served as an Associate Editor for IEEE Transactions on Circuits and Systems I and for IEEE Signal Processing Letters. In addition, he has chaired sessions at international conferences in the areas of communications and VLSI architectures.

Prof. Sobelman has presented short courses at a number of industrial and academic sites. He has authored or co-authored more than 150 technical papers and 1 book, and he holds 12 U.S. patents.

Please sign up and join us on Tuesday, January 5, 2021 at 15:00 (Israel Standard Time).

A link to the Zoom session will be provided after registration.

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