“Digital Predistortion for 5G MIMO Transmitters Using Machine Learning”

Digital predistortion (DPD) has been widely adopted to keep RF power amplifier operating with high efficiency without losing linearity in the exiting 4G systems. It is expected that DPD will continue to be deployed in 5G systems.  However, due to shifting from the single antenna to the multiple-input multiple-output (MIMO) phased array and continuously increased signal bandwidth, system designers face significant challenges in managing power consumption and meeting linearity requirement of  wireless  transmitters.  In this talk, we will discuss how the recently developed machine learning techniques can be utilised to resolve some of the issues in linearizing 5G MIMO systems, including data-clustering assisted DPD for multiple dynamic configurations, model tree-based behavioural model construction and simplified model extraction techniques.

Anding Zhu received the Ph.D. degree in electronic engineering from University College Dublin (UCD), Dublin, Ireland, in 2004. He is currently a Professor with the School of Electrical and Electronic Engineering, UCD. His research interests include high-frequency nonlinear system modeling and device characterization techniques, high-efficiency power amplifier design, wireless transmitter architectures, digital signal processing, and nonlinear system identification algorithms. He has published more than 160 peer-reviewed journal and conference articles. Professor Zhu served as the Secretary of Administrative Committee (AdCom) of IEEE Microwave Theory and Techniques Society (MTT-S) in 2018. He is currently an Elected Member of MTT-S AdCom, the Chair of Electronic Information Committee and the Vice Chair of Publications Committee. He is also the Chair of MTT-S Microwave High-Power Techniques Committee and a Track Editor of IEEE Transactions on Microwave Theory and Techniques.

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“Cryo-CMOS electrical interfaces for large-scale quantum computers” by Prof. Fabio Sebastiano

Quantum computers operate by processing information stored in quantum bits (qubits), which must typically operate at cryogenic temperature. Today the qubits are mostly controlled by conventional electronics working at room temperature. This thermal gap can be readily bridged by a few wires since today’s quantum computers employ only a few qubits. However, practical quantum computers will require more than thousands of qubits, making this approach impractical. A more scalable approach requires operating a complex electronic interface at cryogenic temperature, very close to the quantum processor, eventually in the same package or even on the same chip. Thanks to its high integration capabilities, CMOS is the most viable technology for such a cryogenic interface. In this talk, we will first review the functionalities required to drive and control the most popular qubit technologies, and the requirements on the performance of the electronics. Based on those requirements and the behavior of CMOS devices at cryogenic temperature, several state-of-the-art cryo-CMOS circuits and systems have been designed, both for qubit drive and readout, and we will show their verification with real-world qubits, highlighting challenges and opportunities. Finally, the prospects towards large-scale quantum computers will be outlined, and we will try to answer the questions: Is the electronics a bottleneck for future quantum computers? How will we design cryo-CMOS circuits to tackle this challenge?

Fabio Sebastiano received the B.Sc. (cum laude) and M.Sc. (cum laude) degrees in electrical engineering from University of Pisa, Italy, in 2003 and 2005, respectively, the M.Sc. degree (cum laude) from Sant’Anna school of Advanced Studies, Pisa, Italy, in 2006 and the Ph.D. degree from Delft University of Technology, The Netherlands, in 2011.

From 2006 to 2013, he was with NXP Semiconductors Research in Eindhoven, The Netherlands, where he conducted research on fully integrated CMOS frequency references, nanometer temperature sensors, and area-efficient interfaces for magnetic sensors. In 2013, he joined Delft University of Technology, where he is currently an Associate Professor and the Research Lead of the Quantum Computing Division of QuTech. He has authored or co-authored one book, 11 patents, and over 80 technical publications. His main research interests are cryogenic electronics, quantum computing, sensor read-outs, and fully integrated frequency references.

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“Power efficiency in the next generation of 5G-6G analog front-ends” by Prof. Antonio Liscidini

Nowadays, both digital and analog electronics are reaching fundamental limits that will require revolutionary approaches to satisfy the power/bandwidth requirements of the next generation of data-driven applications.

After a brief overview of the modern wireless transceiver architecture, some key elements that will characterize 5G and 6G networks will be discussed. The talk will continue by analyzing the power efficiency of the analog signal processing by highlighting the presence of a thermodynamic upper-bound which relates dynamic range, bandwidth and power dissipation. Alternative strategies to circumvent this limit will be discusses such as adaptivity, passive time-variant signal processing and quantized analog signal processing. In particular, the latter represents a novel approach where the analog and digital domain are fused together in a more fluid scenario compared to traditional mixed-signal circuits. This operation leads to superior power efficiency and flexibility.

The effectiveness of the proposed solutions will be demonstrated through simulations and measurement results on different prototypes.

Antonio Liscidini received the Laurea (summa cum laude) and Ph.D. degrees in electrical engineering from the University of Pavia, Pavia, Italy, in 2002 and 2006, respectively.

He was a summer Intern with National Semiconductors, Santa Clara, CA, USA, in 2003, studying poly phase filters and CMOS low-noise amplifiers. From 2008 to 2012, he was an Assistant Professor with the University of Pavia and a consultant with Marvell Semiconductors, Pavia, in the area of integrated circuit. In 2012, he moved to the Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada, where he is currently an Associate professor. In 2019 he has become consultant for Huawei Technology Group in the area of RFIC for optical communication. His research interests are focused on analog mixed signal interfaces with particular emphasis on the implementations of transceivers and frequency synthesizers for wireless and wireline communication.

Dr. Liscidini was a recipient of the Best Student Paper Award at the IEEE 2005 Symposium on VLSI Circuits and co-recipient of the Best Invited Paper Award at the 2011 IEEE CICC and the Best Student Paper Award at the 2018 IEEE ESSCIRC. He has served as an Associate Editor for the IEEE Transactions on Circuits and Systems II: Express Briefs (2008-2011) (2017- 2018) and for the IEEE Open Journal of Solid-State Circuit Society (2021), as a Guest Editor for the IEEE Journal of Solid-State Circuits (2013) (2016) and Guest Editor of the IEEE RFIC Virtual Journal (2018). He has been member of the ISSCC TPC (2012- 2017), of the ESSCIRC TPC (2010-2018), and of the CICC TPC (2019-currently). Between 2016 and 2018, he has been a Distinguished Lecturer of the IEEE Solid-State Circuits Society.

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“Embedded Systems Design in the Era of AI” by Prof. Michael Huebner

The increasing demands of complexity, flexibility and self-organization of networked embedded systems require new solutions for the local processor architectures and firmware. This includes the ability to adapt to the requirements of an algorithm e.g. in relation to a sensor value measured by an Cyberphysical System. Artificial intelligence becomes ubiquitous and therefore enters also the domain of embedded systems and enables enormous opportunities in edge computing. This will introduce new degrees of freedom in embedded and Cyberpyhsical systems and is very promising to support the aforementioned demands tremendously. In this talk, possible solutions for next generation embedded systems with AI components will be introduced.

Michael Huebner is a Full Professor and leads the Chair for Computer Engineering at the Brandenburg University of Technology (BTU) in Cottbus, Germany, since 2018.

He is also Vice-President for research and transfer at BTU since December 2020.

He received his diploma degree in electrical engineering and information technology in 2003, his Ph.D. degree in 2007 from the University of Karlsruhe (TH), and did his habilitation in 2011 at the Karlsruhe Institute of Technology (KIT) in the domain of reconfigurable computing systems.

His research interests are in reconfigurable computing and particularly new technologies for adaptive FPGA run-time reconfiguration and on-chip network structures with application in automotive systems, incl. the integration into high-level design and programming environments.

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“An Organic-Photoconductive-Film CMOS Image Sensor’s Advanced Technologies” by Kazuko Nashimura

We have developed a CMOS image sensor with an organic photoconductive film (OPF) laminated on pixel circuits, different from those of a conventional silicon image sensors, in which the organic thin film for photoelectric conversion and the charge storage part for signal charge accumulation are completely independent. In this presentation, we focus on the advantageous features of the OPF image sensor; [1] technology that realizes over 120 dB simultaneous-capture wide dynamic range; [2] global shutter technology achieving high saturation signals per unit square that is 10 dB higher than that of silicon image sensors with the global shutter function, without sacrificing pixel area; [3] RGB-NIR sensor technology capable of controlling NIR sensitivity by simply controlling the voltage applied to the OPF. Moreover, we introduce about 8K4K high resolution sensor technologies with 60fps high frame rate, 450ke- high saturation signals, and the global shutter function at the same time. We believe these features of the OPF image sensor will contribute to leaps in the imaging and sensing fields.

Kazuko Nishimura received the B.E. degree in mechanical engineering from Osaka University, and joined Panasonic Corporation where she engaged in high-speed analog-to-digital converters (ADCs) in 1995. She developed optical communication systems for fiber-to-the-home (FTTH), RF tuners and CMOS image sensors. Currently, she is a manager in Technology Division (R&D Division), Panasonic Corporation and pursues research on the organic photoconductive film (OPF) CMOS image sensors and sensor applications. She serves A-SSCC data converter subcommittee chair and ISSCC Imagers, Medical, MEMS and Displays subcommittee, IEEE SSCS distinguished Lecturer, and the SSCS Adcom. She is a senior member of IEEE.

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“Hardware Security and Safety of IC Chips” webinar by Prof. Makoto Nagata

IC chips are key enablers to a smartly networked society and need to be more compliant to security and safety. For example, semiconductor solutions for autonomous vehicles must meet stringent regulations and requirements. While designers develop circuits and systems to meet the performance and functionality of such products, countermeasures are proactively implemented in silicon to protect against harmful disturbances and even intentional adversarial attacks.

This talk will start with Electromagnetic Compatibility (EMC) techniques applied to IC chips for safety to motivate EMC-aware design, analysis, and implementation. It will discuss IC design challenges to achieve higher levels of hardware security (HWS). Crypto-based secure IC chips are investigated to avoid the risks of side-channel leakages and side-channel attacks, corroborated with silicon demonstrating analog techniques to protect digital functionality. The EMC and HWS disciplines derived from electromagnetic principles are key to establishing IC design principles for security and safety.

Makoto Nagata received the B.S. and M.S. degrees in physics from Gakushuin University, Tokyo, in 1991 and 1993, respectively, and a Ph.D. in electronics engineering from Hiroshima University, Hiroshima, in 2001.. He is currently a professor of the graduate school of science, technology and innovation, Kobe University, Kobe, Japan. He is a senior member of IEICE and IEEE.

His research interests include design techniques targeting high-performance mixed analog, RF and digital VLSI systems with particular emphasis on power/signal/substrate integrity and electromagnetic compatibility, testing and diagnosis, three-dimensional system integration, as well as their applications for hardware security and safety.

Dr. Nagata has been a member of a variety of technical program committees of international conferences. He is chairing the Technology Directions subcommittee for International Solid-State Circuits Conference (2018-present). He is also serving as SSCS AdCom member since 2020. He is currently an associate editor for IEEE Transactions on VLSI Systems (2015-present).

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“Asynchronous Stream Computing for Low Power IoT – Asynchronous Stochastic Computing (ASC), Asynchronous Stream Processing (ASP) and Asynchronous Impulse Radio (AIR) for ubiquitous sensing at the Edge” webinar by Prof. Mircea R. Stan

Asynchronous circuits have many potential advantages over their synchronous counterparts in terms of robustness to parameter variations, wide supply voltage ranges, and potentially low power by not needing a clock, yet their promise has not been translated yet into commercial success due to several issues related to design methodologies and the need for handshake signals. Stochastic computing is another processing paradigm that has shown promises of low power and extremely compact circuits but has yet to become a commercial success mainly because of the need for a fast clock to generate the random streams.
In this talk we will go over three complementary circuit techniques: Asynchronous Stochastic Computing (ASC), Asynchronous Stream Processing (ASP) and Asynchronous Impulse Radio (AIR). These techniques combine the best features of asynchronous circuits with the best features of stochastic computing to enable extremely compact and low power IoT sensing nodes. Together they can fulfill the promise of smart dust, a concept that was ahead of its time and yet to achieve commercial success.

Mircea R. Stan is the Virginia Microelectronics Consortium (VMEC) professor at the University of Virginia. He is teaching and doing research in the areas of high-performance low-power VLSI, Processing in Memory, temperature-aware circuits and architecture, Cyber-Physical Systems, spintronics, and nanoelectronics. He leads the High-Performance Low-Power (HPLP) lab and is an associate director of the Center for Automata Processing (CAP). He received the 2018 Influential ISCA Paper Award, the NSF CAREER award in 1997 and was a co-author on best paper awards at ASILOMAR19, LASCAS19, SELSE17, ISQED08, GLSVLSI06, ISCA03 and SHAMAN02 and IEEE Micro Top Picks in 2008 and 2003. Prof. Stan is a fellow of the IEEE, a member of ACM, and of Eta Kappa Nu, Phi Kappa Phi and Sigma Xi.

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“Closed-Loop Neuromodulation”

Facing a growing number of patients with neurological disorders, there are only limited therapeutic pharmacological measures which provide only temporary and mild amelioration of the devastating symptoms of these disorders. The use of electrical stimulation of the brain is a treatment option for patients with severe treatment-resistant disorders. Current deep-brain stimulation (DBS) approaches are hindered by inadequate technology that is low-precision and bulky, power-inefficient, and of limited diagnostic utility. The seminar will discuss a high-precision implantable neurotechnology for closed-loop neuromodulation of functional networks of the human brain. Key features of the technology are: 1) sensing from a high number of channels, 2) sensing concurrent with stimulation for true closed-loop operation, and 3) real-time secure wireless data telemetry. The proposed neurotechnology could revolutionize brain therapies in efficacy, size and cost of medical implants.

Dejan Marković is a Professor of Electrical and Computer Engineering at the University of California, Los Angeles (UCLA). He is also affiliated with UCLA Bioengineering Department, Neuroengineering field. He completed the Ph.D. degree in 2006 at the University of California, Berkeley, for which he was awarded 2007 David J. Sakrison Memorial Prize. His current research is focused on implantable neuromodulation systems, domain-specific compute architectures, and design methodologies. Dr. Marković co-founded Flex Logix Technologies, a semiconductor IP startup, in 2014, and helped build foundational technology of Ceribell, a medical device startup. He received an NSF CAREER Award in 2009. In 2010, he was a co-recipient of ISSCC Jack Raper Award for Outstanding Technology Directions. He also received 2014 ISSCC Lewis Winner Award for Outstanding Paper. Prof. Markovic is an IEEE Fellow.

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“Circuits and architectures with ultra-wide power-performance adaptation – going way beyond voltage scaling”

Wide power-performance adaptation down to nWs has become crucial in always-on nearly real-time and energy-autonomous SoCs that are subject to wide variability in the power availability and the performance target. Wide adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of SoCs having an extremely wide performance-power scalability and adaptation, so that they can relentlessly operate without interruption in spite of the highly-uncertain power availability.

In this talk, new directions to drastically extend the performance-power scalability of digital, analog and power management circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path in the digital sub-system. New directions to achieve full-system coordinated power-performance scaling are also discussed. Silicon demonstrations and trends in the state of the art of battery-light, battery-less and battery-indifferent SoCs are illustrated to quantify the benefits offered by wide power-performance adaptation, identifying opportunities and challenges for the decade ahead. Finally, an always-on mm-scale integrated system that operates uninterruptedly when solely powered by moonlight is demonstrated, paving the way to a new generation of always-on systems with little to no battery.

Massimo Alioto is a Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group, and is the Director of the Integrated Circuits and Embedded Systems area and the FD-FAbrICS research center on intelligent&connected systems. He held positions at the University of Siena, Intel Labs CRL, University of Michigan Ann Arbor, University of California Berkeley, EPFL – Lausanne.

He is (co)author of 300 publications on journals and conference proceedings, and four books with Springer. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies.

He is the Editor in Chief of the IEEE Transactions on VLSI Systems, Distinguished Lecturer for the IEEE Solid-State Circuits Society, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012), as well as Distinguished Lecturer (2009-2010) and member of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2023, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.

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“A Flexible vision for RF ICs” by Dr. Matan Gal-Katziri

Flexible high-speed systems and architectures have promising and exciting applications at the intersection of communications, imaging, medicine and deployable arrays. The flexibility is expressed in terms of electrical reconfigurability, flexible circuit board materials, and lightweight, bendy interconnects between remote array elements. In this talk I will present my work at Caltech’s High-speed and holistic IC laboratory in developing such systems. Two key elements in our flexible schemes are the utilization of highly functional RFICs to minimize rigid component count, and a holistic, modular design approach which is crucial to future size scaling. Through the talk I will present several exemplary architectures for space, power transfer, communication and sensing applications, and will discuss the high-level considerations, implementation, challenges, and potential uses of such systems.

Matan Gal-Katziri received the B.S. degrees in Physics and Electrical Engineering from Ben-Gurion University, Beer-Sheva, Israel in 2009, and M.S. and Ph.D. degrees in electrical engineering from Caltech, Pasadena, CA, USA, in 2016 and 2020, respectively. He is currently a postdoctoral research associate in the department of electrical engineering at Caltech, Pasadena, CA. He is a part of Caltech’s Solar-Space Power Program RF design team, where his work on flexible arrays sheets has won the 2020 IMS advanced practice award. His research interests are high-frequency, integrated, and large-scale systems for medical, environmental, industrial and communications applications.

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