ACRC Research Retreat will take place at the Ein Gedi Hotel on February 24-25, 2025.

The participants of the retreat will include faculty members, students, and representatives from the industry.

The idea is to share knowledge and foster collaborations.

About the Retreat: The retreat will bring together faculty members, graduate students, and industry representatives for two days of knowledge sharing, networking, poster sessions, and discussions.

Following the success of our previous retreat, where participants highly appreciated the opportunity to exchange ideas and build connections,

we are excited to expand this initiative with new cross-disciplinary themes.

Main Topics: This year, the retreat will focus on two pivotal areas:

Cyber-Security and Geo-Security

Machine Learning in Hardware

The program will feature keynote talks, research presentations, panel discussions, and ample opportunities for informal networking, aiming to inspire innovative collaborations and advancements in these critical fields.

Registration: https://forms.office.com/r/5Y7617LzLK

Further details will be provided later.

For any inquiries or suggestions, feel free to contact me.

Looking forward to seeing you there and making this retreat a resounding success together!

Date: 4th December, 2024

Time: 18:00 – 19:30 Israel Time

Language: English

Register Here

Abstract: 

Future wearable devices and other deployed sensor systems, including smart agriculture or environmental monitoring, will require new approaches for long-term powering and operation that avoid individual battery recharging. One approach is the use of thermoelectric energy harvesting, where energy is extracted from thermal gradients using a solid-state thermoelectric generator (TEG). Even centimeter-scale TEGs can provide microwatts of power from small temperature gradients, such as body heat, but they present a number of challenges in terms of low-voltage, highly-efficient energy conversion at the output.

In this talk, I will present recent work in low-voltage energy harvesting applied to wearable devices, including some of our own low-level improvements in DC-DC converters and complete thermoelectric energy harvesting solutions – including true battery-less, wearable bioelectronic sensors powered by body heat. I will also present a number of ultra-low-power (ULP) sensor readout interface circuit approaches that enable ULP (<10µW) read-out for resistive-, voltage-, and current-domain sensors, such as temperature, pH, and electrochemical reactions. Together, thermoelectric energy harvesting combined with ULP sensors and read-out ICs are a promising avenue for powering wearable devices using body-heat energy harvesting.

Bio: 

Matthew Johnston received the B.S. degree in electrical engineering from the California Institute of Technology in 2005, and the M.S. and Ph.D. degrees in electrical engineering from Columbia University in 2006 and 2012. He was a Co-Founder and Manager of Research with Helixis, Carlsbad, CA, a Caltech-based spinout developing instrumentation for real-time PCR, from 2007 to its acquisition by Illumina in 2010. From 2012 to 2013, he was a postdoctoral scholar with the Bioelectronic Systems Lab at Columbia University. He also worked as an Associate at a life sciences venture capital firm in New York City.

Dr. Johnston joined Oregon State University in 2014, where he is currently an Associate Professor with the School of Electrical Engineering and Computer Science. His current research interests include the integration of sensors and transducers with silicon CMOS integrated circuits, lab-on-CMOS platforms, ultra-low-power sensor electronics, stretchable circuits and systems, bio-energy harvesting, and low-power distributed sensing.

Dr. Johnston was the recipient of the 2020 Semiconductor Research Corporation (SRC) Young Faculty Award, the 2021 Oregon State University College of Engineering Faculty Teaching Excellence Award, and the 2021 Oregon State University Provost Fellowship. He is currently an Associate Editor of the IEEE Transactions on Circuits and Systems II, and he has also served as an Associate Editor for the IEEE Open Journal of Circuits and Systems and the IEEE Transactions on Biomedical Circuits and Systems.

The webinar is free but registration is required. Zoom link will be sent after registration. 

Register Here

Date: November 20, 2024

Time: 17:30 – 19:00 Israel Time

Speaker: Prof. Seokbum Ko, University of Saskatchewan, Canada

Registration form

Abstract:

Deep learning can provide superior performance in many fields of applications. However, the cost of implementing deep learning models in practical applications is expensive. Deep learning models are both computation intensive and memory intensive. Computation is an important aspect for deep learning. It can determine the latency that is how fast the results can be obtained. In this seminar, computer arithmetic for deep learning will be discussed. This lecture will start with discussing the computation requirements of deep learning models and layers. Then, several computer arithmetic designs for deep learning in the literature will be used as examples. Finally, future trends of computer arithmetic for deep learning computation will be discussed.

Posit is designed as an alternative to IEEE 754 floating-point format for many applications. It has non-uniformed number distribution, and it can provide a much larger dynamic range than IEEE floating-point format. These make posit especially suitable for deep learning applications. In recent years, more and more posit based deep learning hardware accelerators appear in the literature. In this lecture, the basics of posit format and the corresponding posit-based arithmetic units available in the literature, including adder, multiplier, multiply-accumulate unit, and quire operator, will be discussed. Then, several posit-based deep learning processors for deep learning inference and training will be discussed. Finally, the trends and challenges of posit arithmetic units and posit based deep learning processors will be discussed to motivate more related research works.

Deep learning applications will be shared with the audience.

Bio: 

Seokbum Ko is currently a Professor at the Department of Electrical and Computer Engineering and the Division of Biomedical Engineering, University of Saskatchewan, Canada. He received his PhD from the University of Rhode Island, USA in 2002.

His areas of research interest include computer architecture/arithmetic, efficient hardware implementation of compute-intensive applications, deep learning processor architecture and biomedical engineering.

He is an IEEE Cicuits and Systems Society Distinguished Lecturer (2024-2025), a senior member of IEEE circuits and systems society and an associate editor for IEEE TVLSI, IEEE TCAS-II, IEEE Access and IET Computers & Digital Techniques. He is an active member of IEEE CAS Technical Committee, IEEE P3109, IEEE754-2029, IEEE Domain-Specific Accelerators Standarads Committee and IEEE Emerging Processor Systems Standards Committee. He was an associate editor for IEEE TCASI (2019-2021).

The webinar is free but registration is required.

Zoom link will be sent after registration. 

Register Here

Date: September 30, 2024

Time: 16:00 – 17:30 Israel Time

Register here

Abstract

Cryptographic cores such as Advanced Encryption Standard (AES) protect sensitive data algorithmically but are vulnerable to attacks using side-channel information. Malicious attackers can analyze a crypto-core’s power consumption and EM emission (called side channel leakage) while encrypting and revealing the sensitive key of the crypto-core non-invasively and at a low cost. Several approaches have been explored to improve security robustness against these side-channel attacks (SCA). Power management-based techniques are promising as they directly alter the current and EM signatures to weaken the correlations between the compute activity and current/EM signatures.

In this seminar, I shall provide an overview of the recent power management techniques for SCA resilience. I shall present our ongoing work on power management-based techniques such as (i) Galvanic isolation, which separates the encryption current loop from the external VCC/VSS pins, ultimately providing orders of magnitude SCA improvement, (ii) Power delivery approaches against fine-grain EM SCAs (iii) Voltage stacking utilizing single current loop for multiple compute activities thereby reducing the correlation between the current/EM loops and underlying compute activity. Finally, I will conclude the seminar by highlighting the SCA issues arising from adopting imminent power delivery technologies such as buried power rails and back-side power delivery in advanced CMOS technologies.

Bio

Jaydeep Kulkarni is an Associate Professor in the Chandra Department of Electrical and Computer Engineering and a Fellow of Silicon Labs Endowed Chair at the University of Texas at Austin. His current research is focused on machine learning hardware accelerators, in-memory computing, emerging nano-devices, heterogeneous and 3D integrated circuits, hardware security, and cryogenic computing. This research has been recognized with the NSF CAREER, SRC Innovator, Intel Rising Star, and Micron Foundation faculty awards. He has served as a Distinguished Lecturer for IEEE SSCS, CAS, and ED societies and as a TPC member for VLSI Symposium, CICC, ASSCC, DAC, ICCAD.

Important: the webinar is free of charge but registration is required

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Abstract 

In this lecture, the variability impact, compensation techniques, and variability-aware neural architectures are discussed. Variability and paracitics pose significant challenges in ensuring accurate multiply and accumulate (MAC) computations emulated with a crossbar. In most neural networks, the MAC forms the core computing module to implement a neuron and, consequently, neural networks. The analog MAC blocks are particularly susceptible to variability and parasitics, which can result in inaccuracies in the computation process. Therefore, developing techniques to mitigate these challenges is crucial for the successful implementation of variability averse mixed-signal neural architectures.

Bio

Alex James is the dean of academics and full-professor of AI hardware at Digital University Kerala; and CTO of India Graphene and Engineering Innovation Centre (a section 8 company). James received his PhD from Queensland Micro and Nanotechnology Centre, Griffith University, Australia. He heads the Maker Village, one of the largest electronic hardware incubators in India with over 80 electronics startups. He heads the Centre for excellence in Intelligent IoT Sensors, and India Innovation Centre for Graphene. He is the founding director board member of India’s first Digital Science Park. He has spun out multiple startup companies from his research group; published more than 200 papers. For the last two decades, he worked in the areas of board design, signal integrity and mixed signal design in Industry and in the area of AI hardware and systems in academia. He has taught more than 60 courses, in the areas of chip design and AI. He was an associate editor for IEEE TCAS1 (2018-2023), and IEEE OJCAS (2023).   He got the IEEE Kerala Section Best Researcher Award (2022), IEEE CASS Best Associate Editor for IEEE TCAS1 (2020-2021), Kerala State Higher Education Council Award 2022 – Kairali Gaveshana Puraskaram from the Kerala government, and 2024 IEEE Transactions on Circuits and Systems Guillemin-Cauer Best Paper Award.  First chair of IEEE CASS Kerala, which won the 2023 IEEE Circuits and Systems Regional Chapter-of-the-Year Award: Region 10 and 2024 IEEE Circuits and Systems Global Chapter-of-the-Year Award.  He is a member of SIG AgriFood and IEEE CASS Technical Committees on Nonlinear Circuits and Systems, Nonlinear Circuits and Systems Technical Committee (NCAS TC), Cellular Nanoscale Networks, and Memristor Array Computing. He is Associate Editor in Chief of IEEE Open Journal of Circuits and Systems (2024-2025) and Associate Editor of IEEE Access, Frontiers in Neuroscience, IEEE Transactions on Biomedical Circuits and Systems and IEEE Transactions on Circuits and Systems for Artificial Intelligence. He is an IET, BCS, and HEA Senior Fellow.

Date & Time: July 22, 2024, 11:00 – 12:30 Israel Time

Important: The webinar is free but registration is required. Register here

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Shai Cohen

The future? Hardware! A Personal Journey

Join Shai Cohen, co founder of Mellanox and proteanTecs on a fascinating journey through the dynamic world of hardware engineering and entrepreneurship In this presentation, Shai will describe the milestones of his career alongside significant advancements in the chip industry, from the early days of the personal computing revolution, through the flourishing of the server farm industry, IoT, and AI, to the advanced innovations of today and tomorrow Through stories from his experience at Intel, founding Mellanox, and leading proteanTecs Shai will demonstrate how engineering innovation and entrepreneurship are changing our world Join this talk to learn how you can lead and make an impact through hardware.

Shai Cohen, co-founder of Mellanox and proteanTecs is a seasoned entrepreneur in the chip industry with extensive experience in managing and building tech companies from their inception Since 2017 he has served as the CEO of proteanTecs a pioneer of deep data analytics for monitoring the health of electronic systems throughout their lifecycle, from manufacturing stages to ongoing market use Before founding proteanTecs Shai co founder of Mellanox, a global leader in InfiniBand and Ethernet technologies for high speed data transfer between servers and storage systems, a company later acquired by Nvidia As COO of Mellanox, he oversaw all operational and manufacturing functions and led research and development activities His professional journey began at Intel, where he was a senior team member in the Pentium processors department and a circuit design manager in the storage controllers group Shai holds a Bachelor’s degree in Electrical Engineering with honors from the Technion Israel Institute of Technology

Date: July 3, 2024, Wednesday

Time: 12:30 – 14:30 Israel Time

Location: 1003 Meyer Building

Register Here

Calling all members of the Israeli computer hardware community!

The Architectures & Circuit Research Center (ACRC) invites you to a day of exploration, networking, and collaboration at our ACRC Research Day on July 1st, 2024.

 Register Here

Agenda:

16:00    Gathering

16:15    Greeting

16:20    Academia-Industry Panel, hosted by Prof. Avinoam Kolodny

    Topic: How AI/ML is Affecting Computer Hardware Development and What Can We Expect in the Future?

    Participants:       

        Prof. Shahar Kvatinsky, ECE Technion

        Rony Friedman, Apple

        Ofri Wechsler, Google

        Shlomit Weiss, Former Intel

        Dr. Ofer Shacham – Majestic Labs

        Michael Kagan, NVIDIA

17:05     ACRC Award Ceremony

    Celebrate excellence! We will be recognizing the outstanding research achievements of graduate students.

17:20     Apple’s Tape-out Project Award Ceremony

    Applaud the brilliance of the next generation!

17:30     Graduate Student Research Poster Display

    Engage with the future of hardware innovation! Interact with graduate students from various Israeli universities and explore their cutting-edge research through interactive poster displays.

This event presents a unique opportunity to:

• Gain insights into the latest advancements at the intersection of AI and computer hardware.
• Network with fellow professionals from academia and industry.
• Discover promising new research directions pursued by talented graduate students.
• Foster collaborations that pave the way for groundbreaking developments in computer hardware.

Don’t miss this chance to connect, learn, and shape the future of computer hardware!

RSVP:

For registration and further details about the event schedule and location –  register here

We look forward to seeing you there!

Target Audience:

This invitation is extended to all researchers, engineers, students, and professionals with an interest in computer hardware in Israel.

 Register Here

Biography

Dr. Assaf Shappir, a Talpiot graduate, received his B.Sc. degree in physics and mathematics from the Hebrew University of Jerusalem, Israel, in 1993 and M.Sc. and Ph.D. degrees in electrical engineering (physical electronics) from the Tel Aviv University, Israel, in 1999 and 2004 respectively. The Ph.D. thesis focused on redistribution of localized trapped charge in the oxide–nitride–oxide gate dielectric stack of the NROM nonvolatile memory device.
Dr. Shappir is a semiconductor veteran with over two decades in the Industry, including in Saifun Semiconductors, where he reached the position of Vice President of Technology Development, Intel and Apple. 

 Dr. Shappir has published 9 scientific papers, 21 conference papers, coauthored 2 book chapters and received 32 patents to date. 

Abstract

Demand for fast storage is growing at an exponential rate, with solid state non-volatile memory (NVM) being the only viable solution. System memory architecture is based on the principle of locality, with frequently accessed data being kept closest to the CPU and a trade-off in cost-performance is practiced using the various memory technologies. NAND Flash is unrivaled in the fast mass storage domain and thus, together with DRAM, has become an entrenched technology. 

In this talk I will review NAND Flash memory, from the underling physics of the basic memory cell, through array operation and the dominant reliability mechanisms. Next I will introduce 3D NAND, where memory cells are vertically stacked on top of each other, enabling a continuous density increase, as required to meet the growing market demand. Finally I will review NAND challenges and their storage system solutions,  including the use of error correction codes (ECC), as well as memory signal processing (MSP) techniques and memory management and redundancy schemes. My talk will conclude with a future outlook and the challenges ahead. 

Date: 02/06/2024

Time: 16:00 – 17:30 Israel Time

Important: The webinar is free but registration is required. Register here

For more details and updates on the series of “ACRC Semiconductor Webinars” please follow our newsletters and our website