Category: Course

Brief RFIC seminar

Supervisor: Prof. Avinoam Kolodny

Place: Auditorium Floor 10, Electrical Engineering Building, Technion

Date: 25.1.10

Abstract:

Brief RFIC seminar

25.1.10

Floor 10, Room1007 Electrical Engineering Building, Technion

 

 

13:30 – 13:45 Reception & Light Refreshments

 

14:00 – 14:30 Dr. Christopher D. Hull

RF transceiver from 3.x towards 4G/ OFDM based systems

 

14:30 – 15:00 Dr. Ofir Degani

Past present and future CMOS Power amplifiers for Wireless

Communications

 

15:00 – 15:30 Coffee Break

 

15:30 – 16:00 Mr. Emanuel Cohen

60 GHz system and components in CMOS for low power compact

Phase Array applications Open discussion- 30 min

 

16:00 – 16:30 Discussion

 

Power Supply Issues in VLSI Systems

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 18.7.10

Abstract:

ACRC Workshop on Challenges and Recent Research in On-Chip Power Delivery

July 18, 2010
Technion, EE building, Auditorium 1003 (10th floor)

Goals: The core issues in on-chip power delivery will be discussed, and related research problems outlined. Some examples of specific research results in the area of on-chip DC-DC conversion and algorithms for efficient IR drop analysis will also be described.
Participants: Engineers from ACRC companies, graduate students and researchers engaged in various aspects of power supply subsystems (e.g. voltage conversion, regulation, on-chip power delivery, power management).

Agenda:
09:30 – 10:00   Registration and refreshments
10:00 – 10:45   Prof. Eby Friedman (Technion)
Introduction/Tutorial: Challenges of Power Delivery
in VLSI Systems.
10:45 – 11:15   Dr. Michael Zelikson (Intel)
System-on-Chip Power Delivery Management – Goals,
Trends and Issues.
The main principles of a modern power delivery
system, possible development directions, anticipated
challenges and interes/files/2018/06/Challenges-of-Integrated-Systems-Power-Delivery-Management_-back.pdfting research directions.
Integrated Circuit Power Management Platforms incorporate
logic and analog blocks together with high voltage and
current power drivers on the same chip. This combination
allows serving a host of applications ranging from power
management in portable devices, power delivery in computer
motherboards through dc dc motor drives and to LED drivers
in street lighting and TV screens.
12:00 – 12:30   Eitan Rosen (Marvell)
Local and Global Investigation of On-chip Power
Simulations of Local and Global Power issues enable understanding
of issues and Power grid and de-coupling capacitors methodology
development.

12:30 – 13:00  Nimrod Ben Ari (Zoran)
 Zoran On-chip Distributed Power Switch
Zoran Power Switch methodology and implementation, including
supporting peripheral circuits, And silicon results.

13:00 – 13: 30   Lunch Break

13:30 – 14:00   Gregory Sizikov (Intel)
Efficiency Considerations for On-chip DC-DC Buck Converters
An analytic method to evaluate frequency dependent losses in on-chip
DC-DC buck converters will be described. The analytical model will
be used for optimizing switching frequency and for minimizing losses
at light and heavy loads.

14:00 – 14:30   Dr. Aharon Unikovsky (Tower)
 A bandgap reference circuit for wide voltage range applications
A bandgap circuit that works in a voltage range of 4V up to 42V
with a very low current consumption and high PSRR.

14:30 – 14:45   Coffee Break

15:00 – 16:00    Panel/Brainstorming session: Open research problems and development directions in VLSI power supply management

16:00 – 16:15   Conclusion

You are invited to a guest lecture after the seminar:
16:30-17:30 Dr.Ingmar Kallfass
The use and benefit of modern active millimeter-wave monolithic integrated circuit (MMIC) technology in high resolution sensing, imaging and high data rate wireless communication applications will be discussed. State-of-the-art in millimeter-wave low-noise and solid-state power amplification is briefly covered. Examples of MMICs based on state-of-the-art metamorphic high electron mobility transistor (mHEMT) technology with gate lengths down to 35 nm and cutoff frequencies fT of over 500 GHz and fmax of more than 700 GHz will be presented. A focus is on the multifunctional integration of analog frontend receivers and transmitters as well as frequency multipliers covering the entire millimeter-wave range up to and beyond 300 GHz. Furthermore, an ongoing Technion – Fraunhofer cooperation in the field of high-speed analog-to-digital converters based on InP hetero-bipolar transistor technology is introduced.

Variation and Low Voltage Digital Circuit Design

Supervisor: Professor David Harris

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 30.12.10

Abstract:

Variation and Low Voltage Digital Circuit Design

Professor David  Harris

  Dep. of Engineering Harvey Mudd College in Claremont, CA.

30.12.10

Auditorium floor 10

This course addresses the challenges of nanometer circuit design arising from variation and low-voltage operation.  The course begins with a review of the sources of variation and the impact on delay, energy, and functionality.  It examines back-of-the envelope statistical analysis techniques to rapidly assess the impact of variation.  Variation effects are accentuated for circuits running at low voltage, particularly in applications such as embedded sensing and dynamic voltage scaling where energy efficiency is critical.  The course describes methods and limits of low-voltage circuit design, including combinational logic, registers, and SRAM design.  Resilient sequencing elements such as Razor and DSTB are particularly interesting because they can reduce the guard bands required to accommodate variation in DVS systems.

 

David  Harris is a Professor of Engineering at Harvey Mudd College in

Claremont, CA.  Prof. Harris received his Ph.D. from Stanford University and his S.B. and M.Eng. degrees from MIT. He has designed circuits at Intel, Hewlett-Packard, Sun Microsystems, and elsewhere.

His research interests include high-performance and low-power digital circuit design, arithmetic, and microprocessors.  Prof. Harris is the co-author of CMOS VLSI Design, Logical Effort, and two other books in the field.

Agenda

08:30 – 09:00 Registration

09:00 – 10:30 Lecture

10:30 – 10:45 Coffee Break

10:45 – 13:00 Lecture

13:00 – 14:00 Lunch Break

14:00 – 15:30 Lecture

15:30 – 15:45 Coffee Break

15:45 – 17:00 lecture

The seminar is free of charge to ACRC members, Intel, Zoran, Marvell, Mellanox.

Others will be charged 500 Shekels+VAT for participating in the seminar.

Course Material

Analog and Mixed-signal Integrated Circuit Design

Supervisor: Prof. Zeljko Ignjatovic

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 15.2.11

Abstract:

Analog and Mixed-signal Integrated Circuit Design

Can we describe analog and mixed-signal circuits as telecommunication channels and determine fundamental limits utilizing Information theory tools?

Professor Zeljko Ignjatovic, University of Rochester

15-17.2.11

Technion, EE building, Auditorium 1003 (10th floor)

Academic organizers:  Prof. Eby Friedman and Prof. Avinoam Kolodny

Please, Register Online!

Course description and material: This course will discuss the circuitry, algorithms and architectures used in analog and mixed-signal mode CMOS integrated circuits, provide practical considerations and detailed design examples . In addition, information theoretical concepts closely related to the design of A/D converters will be discussed and their fundamental resolution-bandwidth limits will be presented. The discussion of the following topics is planned:

Agenda

February 15th

 

08:30 – 09:00 Registration

09:00 – 10:30 Introduction to Switched Capacitor (SC) Circuits and basic building blocks

10:30 – 10:45 Coffee Break

10:45 – 13:00 First order and biquad SC filters

13:00 – 14:00 Lunch Break

14:00 – 15:30 High-order SC filters and Non-ideal effects

15:30 – 15:45 Coffee Break

15:45 – 17:00 Other SC stages and Introduction to Sigma-delta A/D converters

February 16th

 

09:00 – 10:30 Noise shaping, MASH structurs and Non-ideal effects

10:30 – 10:45 Coffee Break

10:45 – 13:00 Higher order Sigma-delta Topologies

13:00 – 14:00 Lunch Break

14:00 – 15:30 Spread-spectrum Technique in Sigma-delta ADC

15:30 – 15:45 Coffee Break

15:45 – 17:00 Noise in SC circuits and Sigma-delta ADC; Turbo-code A/D converters

February 17th

 

09:00 – 10:30 CMOS Image Sensors

10:30 – 10:45 Coffee Break

10:45 – 13:00 Pixel designs in CMOS image sensors

13:00 – 14:00 Lunch Break

14:00 – 15:30 Image sensor readout methods with global feedback – improving readout speed and noise

15:30 – 15:45 Coffee Break

15:45 – 17:00 Fully digital image sensors utilizing pixel level Sigma-delta A/D converters

 

The seminar is free of charge to ACRC members, Intel, Marvell, Mellanox, Samsung, Zoran.

Others will be charged 1500 Shekels+VAT for participating in the seminar.

The course is open free of charge for EE students (undergraduate and graduate).

3-dimensional integration of VLSI circuits – technical, challenges and opportunities

Supervisor: Prof. Eby Friedman

Place: Technion, EE building, Auditorium 1003 (10th floor)

Date: 24.2.11

Abstract: 

You are kindly invited to a Workshop on :

3-dimensional integration of VLSI circuits – technical,  challenges and opportunities

Thursday, 24 Feb 2011, 14:30-17:30

Auditorium Floor 10

 

 

14:15 – 14:30 Registration & Light Refreshments
14:30 – 15:10 Recent Research in 3-D Circuit Design and Related Test Circuits
Prof. Eby G. Friedman, University of Rochester, NY, USA
15:10 – 15:50 Variability Issues in 3-D Clock Distribution Networks
Prof. Vasilis Pavlidis, EPFL, Switzerland
15:50 – 16:10 Coffee Break
16:10 – 16:50 Design and Modeling Methodology of Vertical Interconnects (TSV, mC4…) for 3DI technologies in IBM
Dr. David Goren, IBM, Israel
16:50 – 17:30 Cost Effectiveness of 3D Integration Options
Prof. Dimitrios Velenis, IMEC, Belgium

Design considerations and basic analysis for Inductors and CMOS Radio Frequency Integrated Circuits

Supervisor: Dror Regev

Place: Technion, EE building, Room 1061 (10th floor)

Date: 3.5.11

Abstract:

Design considerations and basic analysis for Inductors and CMOS Radio Frequency Integrated Circuits

Mr. Dror Regev – Terra Freedom Consulting
Dates: May 3,4 2011

Location: Meyer building, Auditorium floor 10

Department of electrical engineering, Technion, Haifa, Israel

This course will start with the design considerations and performance of RFIC inductors and continue with principles, strategies, topologies and challenges in basic CMOS RF circuit design. Simple but powerful analytical tools will be presented to allow designers a better understanding of the challenges and tradeoffs in circuit design preceding CAD circuit simulations. Approaches and tools employed in the seminar may be used as a basis for advanced analysis and design of other RFIC circuits.

Tusday, 3rd of May

08:30-10:00 RFIC Inductors – Inductance basics in Coax, Microstrip and Coupled Micro strips. Layout considerations for Spiral Inductors, Inductor Parasitic, simplified model and Quality factor analysis. Effect of ground and Si substrate on Inductor performance.
10:30-12:00, 13:30-15:00, 15:30-17:00 LNA’s – Common Source Simultaneous Noise and Impedance Matching. Voltage gain analysis of a CS LNA at frequency domain. Electrical stability analysis of a CS LNA and related Impedances. Miller Effect in CS and Cascode transistor introduction. Cascode transistor stability issues. CS IIP3 optimization through gate biasing and the effect of degeneration inductance feedback.

Wednesday, 4th of May

08:30-10:00 Class A PA – maximum linear output power and related optimal load, gain vs. max power out load, device size and operating point considerations, effect of transistor and circuit parasitic, PA stability and stabilization through feedback.
10:30-12:00 Passive Mixer – Modulator in Frequency domain, Time domain analysis, device and operation point optimization, Balanced mixers.
13:30-15:00 Active Mixer – Active design approach and considerations, voltage gain, noise considerations and linearity.
15:30-17:00 VCO-Phase noise and its implications, Oscillator harmonics, Oscillator tanks and oscillation frequency, Tank quality factor and related second order phase noise, Tank design. Methods for injecting energy into the tank, Colpitts Oscillator and it’s phase noise, Colpitts evolution to differential design, VCO Biasing, Large signal analysis, complementary design vs. NMOS design.

Mr. Dror Regev
Short biography

Dror Regev received the BsC degree in electrical engineering from Ben-Gurion University, Israel, in 1987, and the MsC. degree in management from Boston University, in 1994. He is currently teaching CMOS RFIC Circuit Design as an invited lecturer in the Department of Electrical and Computer Engineering, Ben-Gurion University, Israel. From 2006 he teaches RFIC design classes he authored to engineers in the Israeli wireless industry. He is member of IEEE Solid-State Circuits Society.
In 2007, he established an RFIC consulting firm and focused for 3 years on starting up Elipse RFIC Array Devices the first Israeli RFIC design house in Kfar Neter, Israel.
Prior to that, Mr. Regev was with Tower Semiconductors, Israel; Acer Labs, San Jose CA; Intel Haifa, Intel Kiriat Gat; Sierra Microwave Technology, Austin Texas and Elta systems, Israel in senior R&D and Engineering management positions.

The seminar is free of charge to ACRC members, Intel, Marvell, Mellanox, Samsung, Zoran.

Others will be charged 1000 Shekels+VAT for participating in the seminar.

The seminar is open free of charge for EE students (undergraduate and graduate).

Kamran Eshraghian Seminar

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE Fischbach building, Floor 10 Auditorium 1003

Date: 16.6.11

Abstract:

Program: Addressing Technologies Beyond Moore’s Law: the reality of nanoscale devices as part of future System on System Integration

Speaker: Prof. Kamran Eshraghian

Date: 16.6.11

Location: Electrical Engineering Building, Floor 10 Auditorium 1003

Department of Electrical Engineering, Technion, Haifa, Israel

Synopsys: The evolution of SoC (System-on-Chip) and SiP (System-in-Package) introduce a 3rd dimension (3D) that maybe described in terms of a “Volumetric Growth Law” that takes into account the multitechnology nature of integration for a future whereby hyperintegration becomes the new innovation domain. This new frontier is conjectured to move us way beyond Gordon Moore’s 2-D scaling relationship as we begin to uncover new relationships and principles. While the future is becoming more difficult to predict, most likely we could anticipate an accelerating pace of change that span health sciences and intelligent health care, environmental management, smart energy management through to new innovations in man-machine interfaces, processing and communications. This seminar will explore the integration and likely convergence of disparate and significantly different and challenging technologies that are gaining more focus in the quest for a new processing/computing paradigm. The presentation will highlight the inevitability of 3D hyperintegration using technologies that are either in their infancy or those yet to be uncovered through initiatives of material physicists, computational chemists, and bioengineers and will focus upon one such technology such as Memristor, the 4th electronic component conjectured to challenge the perspective and the mind-set that researchers and industry currently may have.

 Schedule:

Morning session 09.00 – 12.00

lunch break,

Afternoon session 13.00 – 15.00

Topics to be covered:

  1. From humble electron to System-on-System (SoS) Integrated domain
  2. Moore’s Law limitations?
  3. Multilayered technology design space
  4. Active substrates
  5. Insert substrate
  6. Multitechnology road map – future product-line inspired by innovations
  7. Disruptive technologies – an introduction to:
  8. Single electron transistor (SET)
  9. Carbon nano tube FET (CNFET)

iii.     Nano-scale nonlinear photonic circuits

  1. Metamaterial domain – negative index materials
  2. Subwavelength nanoparticles
  3. Nanocircuit elements at optical frequencies
  4. RLC based filters – how do they behave
  5. Future of Universal Memory
  6. Evolution of nonvolatile resistive switching memory technologies

vii.     Memristor (memory resistors) – the 4th fundamental circuit element

  1. 3-Dimentional hyperintegration
  2. System-on-Chip (SoC) and System-on-System (SoS) Integration
  3. Non-Moore’s integration
  4. System-on-System (SoS) design space
  5. Multitechnology platform
  6. Volumetric thresholding
  7. Applications
  8. Memristor-based Circuits and System Architectures
  9. Principles of operation and fundamentals
  10. Processing technology
  11. Modeling and design concepts
  12. Characterization and Modeling behavior
  13. Simple model

iii.     More complex models

  1. Memristor-MOS based circuits
  2. Applications


Kamran Eshraghian is best known in international arena as being one of the fathers of CMOS VLSI (Very Large Scale Integration) having influenced two generations of researchers in both academia and industry in silicon based circuits and systems. He obtained his PhD, MEngSc, and BTech, degrees from the University of Adelaide, South Australia and Dr.-Ing e.h., from the University of Ulm, Germany. In 1979, he joined the Department of Electrical and Electronic Engineering at the University of Adelaide, South Australia, after spending some ten years with Philips Research, both in Europe and Australia. In 1994, he was invited to take up the Foundation Chair of Computer, Electronics and Communications Engineering in Western Australia, and became the Head of School of Engineering and Mathematics and Distinguished University Professor and subsequently became the Director of Electron Science Research Institute. In 2004, he became Founder/President of Elabs as part of his vision for horizontal integration of nanolectronics with those of photo-based systems, thus creating a new design domain for system on

Professor Andrea Baschirotto

Supervisor: Prof. Avinoam Kolodny

Place: Technion, EE Fischbach building, Floor 10 Auditorium 1003

Date: 6-8.9.11

Abstract:

A short intensive course on

Low-Voltage Analog CMOS Design

in scaled CMOS technology Circuit


Prof. Andrea Baschirotto, Milan-Bicocca University

 

 

Dates: 6-8 September 2011

Location:  Department of electrical engineering, Auditorium floor 10

Technion, Haifa, Israel

This course will cover the design of mixed-signal integrated circuits to be implemented in scaled CMOS technology, i.e. with device size smaller than 90nm.

The course will start with the description of MOS transistor behavior in scaled technologies, showing that analog performance metrics are typically worse than in longer minimum-size process. Nonetheless, the course will show circuit and system solutions enabling the design of high performance devices in scaled technologies.

  
Tuesday:
08:30-10:00, 10:30-12:00 Basic CMOS operation, CMOS technology scaling trends
13:30-15:00, 15:30-17:00 CMOS technology scaling trends (cont.), Low voltage (LV) operation – LV at transistor  Level
Wednesday:

08:30-10:00, 10:30-12:00LV at circuit level (Opamp design, Basic bandgap design)

13:30-15:00, 15:30-17:00LV at system level (Analog CT filters)

Thursday

08:30-10:00, 10:30-12:00LV at system level (Analog CT filters – cont., SC circuits)

13:30-15:00, 15:30-17:00 LV at system level (A/D Converters)

  The seminar is free of charge to ACRC members, Intel, Marvell, Mellanox,  Zoran.Others will be charged 1500 Shekels+VAT for participating in the seminar.

The seminar is open free of charge for EE students (undergraduate and graduate).

 

 

 

 

 Prof. Andrea Baschirotto, Milan-Bicocca University

 

Short biography

 

Those of you who have not registered in our newsletter list, and are interested in getting emails from the ACRC, please register in Newsletter site.

 

Andrea Baschirotto graduated in Electronic Engineering (summa cum laude) from the University of Pavia in 1989. In 1994, he received the Ph.D. degree in electronics engineering from the University of Pavia.

In 1994, he joined the Department of Electronics, University of Pavia, as a Researcher (Assistant Professor).

In 1998, he joined the Department of Innovation Engineering, University of Lecce, Italy, as an Associate Professor.

In 2007, he joined the Department of Physics, University of Milan-Bicocca, Italy, as an Associate Professor.

Andrea Baschirotto has a long-term experience in microelectronics for what concerns teaching, researching, and industrial designing.

He is teaching regular Academic courses since 1997. He organized the full educational courses for Electronics Engineering (Bachelor, Master, and Ph.D.) at University of Lecce. He uses to give industrial courses since 1996 (in Bosch, STMicroelectronics, ITC-IRST, Conexant, Mikron, etc…). He is a speaker at the MEAD Summer courses held at EPFL (Lausanne – Switzerland). He uses to give short courses or tutorial at the most important conferences (ISSCC, ISCAS, PRIME).

About his research activity, he founded and he is leading the Microelectronics Group at University of Lecce, which is collaborating with several companies and research institutions (IMEC, Infineon, University of Pavia, RFDomus, STMicroelectronics, etc….). His main research interests are in the design of CMOS mixed analog/digital integrated circuits, in particular for low-power and/or high-speed signal processing. He participated to several research collaborations, also funded by National and European projects. He is/has been responsible of some National and Regional projects for the design of ASIC. Since 1989, he also personally collaborated with several companies on the design of mixed signals ASICs, like STMicroelectronics, Mikron, ACCO, ITC-IRST, RFDomus (now GloNav), Conexant, etc….

He has authored or co-authored more than 190 papers in international journals and presentations at international conferences, 6 book chapters, and holds 25 USA patents. In addition, he has co-authored more than 120 papers within research collaborations on high-energy physics experiments.

Andrea Baschirotto was Associate Editor IEEE Trans. Circuits Syst. – Part II for the period 2000-2003, and he is now serving IEEE Trans. Circuits Syst. – Part I as an Associate Editor. He has been the Technical Program Committee Chairman for ESSCIRC 2002 and he was the Guest Editor for the IEEE JSSC for ESSCIRC 2003 and ESSCIRC2007. He was the General Chair of IEEE-PRIME2006 and AACD2008.

He is the member of the Technical Program Committee of several international conferences (ISSCC, ESSCIRC, DATE, etc..). He is serving since several years the ESSCIRC TPC as Data Converter Subcommittee Chairman. He has been the secretary of the European Committee of ISSCC Technical Program Committee. He is an IEEE Senior member. He is the founder and the Chairman of the IEEE Solid-State Circuit Society Italian Chapter.

Zvi Or-Bach

Supervisor: Prof Yitzhak Birk

Place: room 861 Electrical Eng. Building

Date: 21.11.2011

Abstract:

Guest Lecture

You are invited to attend a lecture by

Zvi Or-Bach

President and CEO of MonolithingIC 3d

On:

 

Monolithic 3D – The effective alternative to Dimensional Scaling

 

 

 

The accelerating complexity and cost of dimensional scaling has given birth to “More than Moore”, of which 3D IC is

one of the leading drivers. Recent breakthroughs have added the option of practical monolithic 3D with a 10,000x

higher vertical connectivity. Multiple researchers have reported the potential of 3D IC with rich vertical connectivity to

provide significant average wire length reduction. In fact, some forecast that each device folding could be equivalent to

one process node of dimensional scaling.

We will present several 3D IC flows with their pros and cons, and the future implications.

We will also present how the technology could be apply to related application including:

Memories, Image sensor, Micro-Display and Wafer-Scale-Integration

 

The lecture will take place on Monday, 21/11/2011

at 10:30-11:30  in room 861

Electrical Eng. Building

Technion City

Advanced CMOS Analog Integrated Circuit Design Course

Supervisor: Prof. Boris Murmann

Place: Meyer Building, Electrical Engineering Department,Technion

Date: 01.03.2012

Abstract:

Advanced CMOS Analog Integrated Circuit Design Course

March 1-9, 2012

Room 165, Meyer building, Electrical Engineering Dept. Technion

 

This course provides an introduction to the design of analog integrated circuits in advanced CMOS technologies. The course material combines the analytical treatment and practical design of important circuit blocks with short-channel transistors. Specifically, the student will work toward the design of operational transconductance amplifiers (OTAs) for use in switched-capacitor circuits. Important aspects that will be covered on this route are the gm/ID-based compact modeling in support of systematic design, the treatment of electronic noise, and feedback circuit analysis using the return ratio method.

This course is ideal for students who have already completed the “Linear Electronic Circuits” course at the Technion and wish to deepen their understanding toward advanced design. It will be equally compelling for practitioners in industry who are looking for ways to reposition, further or deepen their careers toward cutting-edge analog IC design.

 

Instructor: Prof. Boris Murmann, Stanford University
Prerequisite: Linear Electronic Circuits http://eecourses.technion.ac.il/044142/ (or equivalent). Knowledge of basic linear system theory, poles and zeros; feedback, basic bipolar and MOS device physics; basic large- and small-signal transistor models.
Required Text: Analysis and Design of Analog Integrated Circuits, 4th Edition, Gray, Hurst, Lewis and Meyer, Wiley, 2001.
Lecture: 28 hours (in English)
Workshops: 10 hours
Circuit Simulation:

Admission :

 

 

 PSpice

The course is free of charge to ACRC members, Intel, Marvell, Mellanox and Zoran.

Non-ACRC members  will be charged 2000 Shekels+VAT.

 

Certificate of accomplishment to be awarded at the completion of the course, passing the final exam and attending all the lectures.

 

 

Course Schedule

Date Topic
Thu, March 1, 2012
09:00-12:3013:00-15:30

16:00-17:30 workshop

 Lecture Day 1

·        Introduction

·        Review of Square Law MOS Model

·        Short Channel Effects

·        Technology Characterization: gm/ID, fT

·        gm/ID-Based Design
Fri, March 2, 2012
09:00-12:00 		 Lecture Day 2

·        Miller Approximation

·        ZVTC Analysis

·        Electronic Noise
Sun, March 4, 2012
09:00-12:3013:00-14:30

15:00-17:00 workshop

 Lecture Day 3

·        Review of Common Gate and Common Drain Stages

·        Differential Pair

·        Current Mirrors

·        Process Variations

·        Mismatch

 
Mon, March 5, 2012
09:00-12:3013:00-14:30

15:00-17:00 workshop

 Lecture Day 4

·        Feedback Circuit Analysis using Return Ratio

·        Stability of Feedback Circuits

·        Fully Differential Circuits

·        Introduction to Switched-Capacitor Circuits

·        Analysis and Design of Operational Transconductance Amplifiers

o   Frequency Compensation

o   Step Response

 
Tue, March 6, 2012
09:00-12:3013:00-15:30

16:00-17:30 workshop

 Lecture Day 5

·        Design for low noise

·        Analysis and Design of Operational Transconductance Amplifiers

o   OTA Variants

o   Systematic design

·        Supply Insensitive Biasing

·        Bandgap References

 
Fri, March 16, 2012 Final Exam

 

The course is free of charge to EE students (undergraduate and graduate) and has a value of two academic credits

Undergraduate students please register at: http://ug.technion.ac.il/

Graduate students please contact Mrs Keren Seker-Gafni at: kerensg@ee.technion.ac.il

For further information please contact Mrs Suzie Eid: suzie@ef.technion.ac.il

 

Please note that there are a limited number of  places available on this course. Registration  does not guarantee you a place in the class.